• 전력전자학회논문지
• /
• 제6권6호
• /
• pp.489-497
• /
• 2001

병렬로 구성되 UPS 사이에 파라미터 불일치에 따른 순환전류와 전압리플이 발생되어지는데, 이들은 전체 UPS 시스템의 고장 및 신뢰성 저하를 유발한다. 본 논문에서는 이러한 문제점들은 Double 위상동동기기와 능동 다중인 터페이스 리액터를 사용하여 해결하였다. 또한 ADSP21061을 사용하여 제어기를 디지털적으로 구현하였다.

• 한국통신학회논문지
• /
• 제8권3호
• /
• pp.83-90
• /
• 1983

N-Path SC追跡濾波器를 可聽周波數이상에서 硏究하였다. 먼저 전체 SC濾波器의 特性을 決定지우는 Filter Cell에 대한 解析으로 電荷方程式과 差等方程式에 의한 解析을 수행하고 커패시터와 스위치만으로 構成된 4-path와 8-path SC濾波器를 提示하였다. 다음 실제로 SC濾波器블록과 PLL블록의 構成으로 4-path와 8-path SC追跡濾波器를 각각 構成하였으며 最大應答의 移動, 커패시터比와 path數에 따른 Q와 利得(dB)의 變動, 追跡範圍등을 考察하였다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2008년도 하계학술대회 논문집
• /
• pp.466-468
• /
• 2008

본 논문에서는 불평형, 고조파, 잡음 등에 의해 왜곡된 3상 전원으로부터 정확한 위상각을 검출하는 PLL(Phase Locked Loop) 방법을 제안한다. 역상분과 고조파를 포함하는 왜곡된 3상 전원을 동기좌표계 d-q축 전압으로 변환하면 기본파 성분에 의한 일정한 d-q축 전압에 역상분과 고조파에 의한 맥동이 포함된 형태의 전압이 된다. 상태관측기는 이러한 전압에서 맥동성분을 제거하고 기본파 전압만 추출하여 이를 동기좌표계 PLL의 입력으로 사용함으로써 왜곡된 전원조건에서도 정확한 위상각을 검출할 수 있다. 시뮬레이션을 통해 제안된 방법의 성능을 검증하였다.

• 한국통신학회논문지
• /
• 제26권10B호
• /
• pp.1353-1359
• /
• 2001

본 논문에서는 위상획득과정과 동기과정에서 trade-off 현상을 향상시킨 듀얼 위상 주파수 검출기를 제안하여 차지펌프 PLL을 설계하였다. 듀얼 위상 주파수 검출기는 상승에지에서 동작하는 POSITIVE 위상 주파수 검출기와 하강에지에서 동작하는 NEGATIVE 위상 주파수 검출기로 구성되어 있다. 제안한 차지펌프는 전류뺄셈회로를 이용하여 전류 부정합을 감소시켰으며, reference spurs와 전압제어발진기의 변동을 감소시킬 수 있도록 구현하였다. 제안한 차지펌프 PLL은 0.25$\mu\textrm{m}$ CMOS 공정을 사용하여 SPICE로 시뮬레이션 하였으며, 그 결과 1.6~1.85GHz의 넓은 동기범위를 나타내었다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2001년도 하계학술대회 논문집
• /
• pp.271-274
• /
• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
• /
• pp.485-487
• /
• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제17권4호
• /
• pp.534-542
• /
• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1999년도 전력전자학술대회 논문집
• /
• pp.189-192
• /
• 1999

The switched reluctance drive system is known to provide a good adjustable speed and torque characteristics. However, acoustic noise and higher torque ripple are drawbacks. These drawbacks show the fact that SRM drive is not operated with mmf current specified for dwell angle and input voltage. Reducing torque ripple and having precise speed control, PLL technique is adopted. The PLL system in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. A TMS320F240 based on the DSP is used to realizing this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.

• 한국통신학회논문지
• /
• 제21권12호
• /
• pp.3069-3085
• /
• 1996

This paper shows an accurate charge-pump PLL model which considers the wave-form distortion in high speed operation of charge-pump PLL, the leakage current in loop filter, and a physical limit in charge-pump. With proposed model of charge-pump PLL, overload and stability are derived theoretically and the results are compared to the conventional model. Unlike the ideal charge-pump PLL that simplifies calculations, it is possible to analyze the transient-state and the steady-state at the same time with proposed accurate model. Thus, charge-pump over load, in the transient-state and the stead-state of charge-pump, is accuragely analyzed and the results are confirmed with simulation.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2001년도 ICCAS
• /
• pp.108.2-108
• /
• 2001

This paper presents the application of adaptive phase-locked loop (adaptive PLL) technique to control the process variable of the process control system. The adaptive algorithm is related to the error. When the error of the system is changed, the adaptive gain will be directly changed according to the error. If the value of the adaptive gain is large, the value of the error will be large. In this experiment, the reference input is 50% step input. The experimental result in controlling the first order lag process by the adaptive PLL shows that the response of the controlled system has no overshoot, short rise time, and zero steady-state error. The experimental result also shows that when the output disturbance enters to the process control system, the adaptive PLL can maintain the stability of the system and the effect of the output disturbance can also be fast rejected. The adaptive PLL has better performance ...