• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권9호
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• pp.461-466
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• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.383-384
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• 2017

분산 발전에 사용되는 PCS는 계통연계 운전 및 독립 운전을 할 수 있어야 한다. 운전 모드 전환 시 발생하는 과도 상태를 최소화하기 위해 무순단 절체 기능이 필요하다. 이 기능을 위해서 계통 이상 유무에 대한 검출이 빠르게 이루어져야하기 때문에 PLL 알고리즘이 중요한 역할을 한다. 본 논문에서는 운전 모드 전환 시 무순단 절체 관점에서 PLL 알고리즘들을 시뮬레이션을 통해 비교하고 이를 바탕으로 적절한 PLL 알고리즘에 대해 고찰한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.136-137
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• 2014

본 논문에서는 계통 전압이 불평형 및 왜곡되었을 경우에 정확한 위상각을 검출 할 수 있는 DSOGI-QSG(dual second order generalized integrator quadrature signal generation)를 이용한 PLL (phase locked loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 DSOGI-PLL 방법과 비교하기 위해, 전압에 불평형 및 왜곡 사고 발생 시 동기각을 검출하는 시뮬레이션을 하였고, 이를 통해 THD가 개선됨을 입증하였다.

• 한국ITS학회 논문지
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• 제11권4호
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• pp.70-79
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• 2012

FMCW 레이더에서 주파수 램프 신호를 발생시키기 위하여 필요한 타입-3 PLL의 설계 가이드를 제시하였다. 그러기 위해서 개루프 전달함수의 크로스오버 주파수를 1 Hz로 정규화 한 조건에서 Pspice 시뮬레이션을 통하여 폐루프 특성을 비교하였다. 결론적으로 타입-3 PLL의 1) 위상여유는 45도로 하고, 2) 두 개의 영점은 같도록 하며, 3) PLL 차수를 높이기 위한 극점은 개루프 전달함수의 크로스오버 주파수보다 10배 정도 크게 할 것을 권한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.80-82
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• 2019

태양광발전과 풍력발전으로 대표되는 분산형 전원이 계통에 연계됨에 따라 계통 사고 발생 시에 계통연계형 인버터에 대한 각국의 계통 규정(Grid code)이 더욱 엄격해 지고 있다. 최근 국외 계통 규정에서는 저 전압 사고뿐만 아니라 영 전압 사고 시에 인버터가 일정 시간 계통 연계를 유지하며 무효전류 출력 기법을 통해 계통 복구를 지원할 것을 요구하고 있다. 계통 사고 시, 사고 전압 잔존량에 따라 무효전류를 정확하게 출력하기 위해 인버터의 PLL(Phase Locked Loop) 제어는 중요하다. 그러나 이러한 PLL 제어의 동적 특성은 계통 사고 순간의 전압 강하 및 사고 위상에 따라 영향을 받게 되고 영 전압 사고에서는 위상 추종이 불가능하기 때문에 복합적인 문제가 나타난다. 본 논문에서는 영 전압 사고에서 사고 위상에 따라 각각 다르게 나타나는 PLL 동적 특성을 시뮬레이션을 통해 분석하였다.

• Macromolecular Research
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• 제8권1호
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• pp.26-33
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• 2000

A series of pH/temperature sensitive polymers were synthesized by copolymerizing N-isopro-pyl acrylamide(NIPAAm) and acrylic acid(AAc) . The influence of polyelectrolyte between poly(allyl amine) (PAA) and poly(L-lysine)(PLL) on the lower critical solution temperature(LCST) of pH/temperature sensitive polymer was compared in the range of pH 2∼12. The LCST of PNIPAAm/water in aqueous poly(NIPAAm-co-AAc) solution was determined by cloud point measurements. A polyelectrolyte complex was prepared by mixing poly(NIPAAm-co-AAc) with poly(allyl amine) (PAA) or poly(L-lysine) (PLL) solutions as anionic and cationic polyelectrolytes, respectively. The effect of polyelectrolyte complex formation on the conformation of PLL was studied as a function of temperature by means of circular dichroism(CD). The cloud points of PNIPAAm in the aqueous copolymers solutions were stongly affected by pH, the presence of polyelectrolyte solute, AAc content, and charge density. The polyelectrolyte complex was formed at neutral condition. The influence of more hydrophobic PLL as a polyelectrolyte on the cloud point of PNIPAAm in the aqueous copolymer solution was stronger than that of poly(allyl amine)(PAA). Although polymer-polymer complex was formed between poly(NIPAAm-co-AAc) and PLL, the conformational change of PLL did not occur due to steric hinderance of bulky N-isopropyl groups of PNIPAAm.

• Biomolecules & Therapeutics
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• 제6권1호
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• pp.14-19
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• 1998

In the present study, we intended to investigate whether cationic polyamines including poly-L-Iysine (PLL) and poly-L-arginine (PLA) induce cytotoxicities to cultured hamster tracheal surface epithelial (HTSE) cells. Confluent HTSE cells were chased for 30 min in the presence of PLL or PLA of different molecular weights. Possible cytotoxicities of PLL or PLA were assessed by measuring both Lactate Dehy- drogenase (LDH) release during treatment and the number of floating cells after treatment and by checking the possible changes on the morphology of HTSE cells during treatment. The results were as follows: in the case of treatment of PLL or rLA of which molecular weight is about 78,000 and 92,000, respectively, (1) there was significant release of LDH during treatment, (2) the number of floating cells were significantly increased after treatment and (3) there were significant changes on the morphology of cultured HTSE cells. However, in the case of PLL or PLA of which molecular weight is under 10,000 (about 9,600 and 8,900, respectively), no significant signs of cytotoxicities mentioned above were detected. We found that cationic polyamines might be non-toxic under specific range of molecular weights and suggest that the cytotoxicity of cationic polyamine might depend on the molecular sizes of each cationic polyamine.

• 한국정보통신학회논문지
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• 제16권12호
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• pp.2716-2724
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• 2012

본 논문에서는 기존의 fractional-N 위상고정루프의 가장 큰 문제점인 fractional 스퍼를 억제하기 위해 위상차-전압 변환기(Phase Difference-to-Voltage Converter : PDVC)를 도입하였다. PDVC는 위상주파수 검출기 출력 신호의 위상차에 따라 전하펌프의 전류량을 조절한다. 제안한 구조는 위상 주파수 검출기(phase frequency detector) 신호들의 위상차가 커지면 전하펌프(charge pump) 전류를 감소시켜 fractional 스퍼를 줄일 수 있는 구조이다. 회로는 1.8V $0.18{\mu}m$ CMOS 공정의 파라미터를 이용하여 HSPICE로 시뮬레이션을 수행하고 회로의 동작을 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.