• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제19권9호
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• pp.1010-1019
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• 2008

In this paper, we present a noise analysis and measurement results of a bio-radar system that can detect human heartbeat and respiration signals. The noise analysis including various phase noise effects is very important in designing the bio-radar system, since the frequency difference between the received signal and local oscillator is very small and the received power is very low. All of the noise components in a bio-radar system are considered from the point of view of SNR. From this analysis, it can be concluded that the phase noise due to antenna leakage is a dominant factor and is a function of range correlation. Therefore, the phase noise component with range correlation effect, which is the most important noise contribution, is measured using the measurement setup and compared with the calculated results. From the measurement results, our measurement setup can measure a closed-in phase noise of a free-running oscillator. Based on these results, it is possible to design a 2.4 GHz bio-radar system quantitatively which has a detection range of 50 cm and low power of 1 mW without additional PLL circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.126-142
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• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권8호
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Korean Journal of Food Science and Technology
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• 제25권6호
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• pp.637-642
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• 1993

Changes in the physicochemical characteristics and triglyceride molecular species of corn oil under the following condition of hydrogenation; temperature $180^{\circ}C,\;H_{2}$, pressure $2.0{\pm}0.3bar$, the amount of Ni catalyst 0.048%(Ni/oil by wt.) and agitation speed 300 rpm. The rate of hydrogenation, expressed as the reduction rate of the iodine value with respect to time, is first order and high (K>0.01). When the reduction rate of the iodine value was 39.9%, hydrogenation time was 30 min, 18:1 was highest(77.06%), thereafter that was decreased and 18:0 increased. In the triglyceride composition, OLL, LLL were reduced markedly in 10 min, thereafter reduced slightly. And PLO, PLL, OLO were eliminated in first 30 min. On the other hand, POO, PLS(CN52) and OOO, SLO(CN54) were increased sharply, and then that showed little change. The melting point(MP) of hydrogenated corn oil were $27.8^{\circ}C\;and\;44.1^{\circ}C$ after 20 min and 60 min, respectively. Trans isomer content increased to 46.8% during 40 mins of hydrogenation and then decreased insignificantly. The solid fat content were linearly increased with hydrogenation time. Accordingly, it is confirmed that this condition of hydrogenation was selective, preferential elimination of polyunsaturated fatty acid went stepwise and trans isomer was formed promotedly. These results suggest that fat modification techniques can be used for practical application.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권7호
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제21권4호
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제38A권8호
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• pp.623-628
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• 2013

The retrodirective array antenna system is operated faster than existing techniques of beamforming due to its less complexity. Therefore, it is effective for beam tracking in the environment of fast vehicle. On the other hand, it also has difficulty in estimating AOA according to multipath environment or multiuser signals. To improve the certainty of estimating AOA), this article proposes hybrid digital retrodirective array antenna systme combined with MUSIC algorithm. In this paper, the digital retrodirective array antenna system is designed according to the number of antenna array by using only one digital PLL which finds angle of delayed phase. And we evaluate the performance of the digital retrodirective array antenna for the high speed tracking application. Performance is studied by simulink when the speed of mobile is 300km/h and the distance between transmitter and receiver is 100m and then we have to confirm the performance of the system in multi path environment. As a result, the mean of AOA (Angle Of Arrival) error is $4.2^{\circ}$ when SNR is 10dB and it is $1.3^{\circ}$ when SNR is 20dB. Consequently, the digital RDA shows very good performance for high speed tracking due to the simple calculation and realization.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제15권2호
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제42권4호
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• pp.864-870
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• 2017

This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using $0.18{\mu}m$ CMOS process and die size was $1.38mm{\times}1.37mm$. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제44권5호
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.