• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.10a
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• pp.41-44
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• 1997

본 논문에서는 뉴로퍼지제어기를 이용한 유도가열기의 시변부하에 대한 적응 정전력 제어를 하고자 한다. 유도가열기의 정전력 조절을 위해 IGBT를 사용한 위상전이형 펄스폭변조(PWM)와 PLL에 의한 부하공진주파수 추종형 펄스 주파수변수(PFM)가 조절되는 공진 고주파 인버터를 유용한 유도가열기를 설명하고, 실험 제작된 유도가열기에서의 부하에 대한 규정 전력 추종이 잘되고 있음이 실제적으로 논증되어졌다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.491-494
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• 2004

Neural Oscillator can be applied to oscillatory systems such as the image recognition, the voice recognition, estimate of the weather fluctuation and analysis of geological fluctuation etc in nature and principally, it is used often to pattern recoglition of image information. Conventional BPL(Back-Propagation Learning) and MLNN(Multi Layer Neural Network) are not proper for oscillatory systems because these algorithm complicate Learning structure, have tedious procedures and sluggish convergence problem. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(phase-Locked Loop) function and by using a simple Hebbian learning rule. And also, Recognition velocity of Korean Character can be improved by using a Neural Oscillator's learning accelerator factor η$\_$ij/

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.12 no.1
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• pp.20-28
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• 2012

We define a language $\mathcal{RS}$, a subclass of the scheduling language $\mathcal{RS}V$ (resource constrained project scheduling with variant processes). $\mathcal{RS}$ involves the determination of the starting times for ground activities of a project satisfying precedence and resource constraints, in order to minimize the total project duration. In $\mathcal{RS}$ ground activities and two structural symbols (operators) 'seq' and 'pll' are used to construct activity-terms representing scheduling problems. We consider three different variants for formalizing the $\mathcal{RS}$-scheduling problem, the optimizing variant, the number variant and the decision variant. Using the decision variant we show that the problem $\mathcal{RS}$ is $\mathcal{NP}$-complete. Further we show that the optimizing variant (or number variant) of the $\mathcal{RS}$-problem is computable in polynomial time iff the decision variant is computable in polynomial time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.433-437
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• 2000

본 논문에서는 데이터 전송용 특정 소출력 무선국용 무선기기의 송수신단의 회로를 설계하고 제작하여 특성을 측정하였다. 주파수 대역은 424.7~424.95MHz이고, 반이중(Half Duplex Communication) 통신방식, PLL Synthesized, 20 Channel, 12.5kHz Channel Bandwidth 그리고 FSK Modulation/Demodulation 방식을 사용하였다. 송신단은 저잡음 증폭기와 전력증폭기를 사용하여 10mW의 출력으로 설계하였고, 발생되는 스퓨리어스를 감쇄시키기 위해 저역통과필터와 공진 회로로 구성하였다. 수신단은 Dual Conversion 방식을 사용하였다. 설계한 결과, 송신단의 출력은 9.71dBm, 스퓨리어스특성 47dBc 그리고 수신단은 감도가 -113dBm에서 Jitter가 $\pm$12.3%로 나타났다.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.38-44
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• 2015

This paper presents the sensorless drive method for mono inverter dual parallel (MIDP) surface mounted permanent magnet synchronous motor (SPMSM) drive system. MIDP motor drive system is a technique that can reduce the cost of the multi motor driving system. To maximize this merit of the MIDP motor drive system, the sensorless technique is essential to eliminate the position sensors. This paper adopts an appropriate sensorless method for MIDP SPMSM drive system, which uses the reduced order observer and phase locked loop (PLL) to reduce the calculation burden. The I-F control method is implemented for start-up and low speed operation. The validity and performance of the proposed algorithm are shown via experiments with 600-W SPMSMs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1120-1135
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• 2005

In this paper, We have design and implement the network synchronization module for NG-SDH system having 120 Gbps capacity. and also evaluate the performance of it. We also propose analyzing algorithm clock characterisrics on NG-SDH node clock based on the evaluation results.

• 전기의세계
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• v.30 no.11
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• pp.717-727
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• 1981

The phase-locked loop technique developed in the 1930's has many advantages when applied to speed control. The speed control and analysis of a three phase induction motor using the PLL are described in this paper. In this system, the phase frequency detector (PFD) compares the actual motor speed from the pulses received from a shaft encoder and desired speed, and the difference adjusts the frequency of the inverter that feeds the motor, and excellent speed regulation in the order of 0.035(%) has been-obtained. A linear continuous model of the drive is developed and system response is analysed using conventional root locus techniques. Various compensating filters and feedback signals are considered and the need for addition of derivative feedback is shown. A sampled data model is used to study the effects of discrete PFD output. Stability limitson speed are predicted. A drive was implimented and experimental results are presented to verify theoretical predictions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.46-51
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• 2006

This paper reports on the effects of silicone oils, used as processing agents, on the recovery of hydrophobicity of silicone rubber. The recovery of hydrophobicity was evaluated by the measuring the contact angle, the surface electrical resistance and SEM. Here, we formed artificial contamination on the surface of samples, which scratched by sand papers and alumina powders. There was small recovery of hydrophobicity on the surface of SIR-A that silicone oil was not added. In both oil-added samples, SIR-B and SIR-C, recovery of hydrophobicity was achieved greatly. The surface of SIR-C showed that a lot of silicone oil was observed due to migration of oil, relatively in comparison with SIR-B. The tendency of recovery of hydrophobicity expressed by contact angle was in a good agreement with electrical property as determined by surface resistivity.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.206-210
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• 2000

본 논문에서는 PLL 주파수 합성기를 이용한 900 MHz 대역의 무선 마이크용 송신기를 설계 및 제작하였다. 위상잡음을 고려한 주파수 합성기는 VCO, Loop Filter 및 RF 중폭부로 구성한 후 HP EEsof ADS ver. 1.3을 이용하여 설계하였다. VCO는 구조가 간단하며 변조가 용이한 직접변조방식을 사용하였으며 Loop Filter는 주파수 합성기의 기준 고조파 성분을 낮추기 위해 수동 3차 필터를 사용하였다. 주파수 대역 928.125 MHz～929.875 MHz 내에서 채널간격 125 kHz를 갖으며 15개의 채널이 되도록 분주비를 설정한 주파수 합성기는 제작 결과, 송신기 출력 9.3 dBm과 위상잡음이 100 kHz에서 -113 dBc/Hz 이하의 위상잡음 특성을 나타내었고 불요주파수 특성은 -80 dBc 이하의 특성을 나타내었다.