• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.29-35
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• 2013

In this paper, we investigate the type and detection methode of spoofing attack, and then analyze the performance of spoofing detection algorithm in GPS L1 signal through the simulation. Generally spoofer is different from the jammer, because the receiver can be operated and not. In case of spoofing the GPS receiver is hard to recognize the spoofing attack and can be operated normally without stopping because the spoofing signal is the mimic GPS signal. To evaluate the performance of spoofing detection algorithm, both the software based spoofing and GPS signal generator and the software based GPS receiver are implemented. In paper, we can check that spoofing signal can affect to the DLL and PLL tracking loop because code delay and doppler frequency of spoofing. The spoofing detection algorithm has been implemented using the pseudorange, signal strength and navigation solution of GPS receiver and proposed algorithm can effectively detect the spoofing signal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Journal of IKEEE
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• v.25 no.4
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• pp.721-727
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• 2021

This paper proposes a UWB (Ultar-wideband) impulse generator using the gated ring oscillator. The oscillator and PLL circuits which generate a several GHz LO signal for the conventional architecture are replaced with the gated ring oscillator. Therefore, the system complexity is decreased. The proposed architecture controls the duty of enable signal, which is used for the head switch of ring oscillator. The control of the duty enables to tun off the oscillator during the guard interval and stop wasting the power consumption. The pulse shaping method using the counter makes the small side lobe and preserves the bandwidth regardless of the change on the center frequency. Designed UWB impulse generator could change the center frequency from 6.0 GHz to 8.8 GHz with a digital bit control, while it preserves the bandwidth as about 1.5 GHz.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1199-1201
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• 2002

Today, the ceramic transformer becomes widely used for the TFT LCD backlight inverter system thanks to its high efficiency and small size. In this paper, a high efficient inverter system for cold cathode flourescent lamp (CCFL) including PLL controller for tuning the PWM frequency to the frequency that the efficiency of the inverter system becomes maximum is proposed. The control IC implementing this feature will be released by Interpion Co. Ltd. in May 2002.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1030-1032
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• 2002

본 논문은 새로운 개념의 방전 플라즈마 소결 접합장비에 적용된 출력펄스 가변형 저전압, 대전류 사이리스터 정류기의 개발에 대하여 설명하고 있다. 6펄스 형태로 개발된 대용량 출력펄스 가변형 정류기는 공냉식으로 제작되어 기존의 대용량 정류기에서 적용한 수냉식보다 구조가 단순하며 최대 l1600A의 출력을 펄스 단위로 반복적으로 차단 및 전류하는 것이 가능하도록 설계되었다. 전류분배를 위한 버스바의 형태는 기구적인 설계만으로 간단히 대전류를 분배할 수 있도록 하였으며 디지털 연산에 의한 PLL 방식으로 입력 전압의 동기가 필요하지 않다. 시뮬레이션과 실물부하를 연결한 실험을 통해 제안한 방법 및 성능의 우수성을 조사하였다.

• Journal of Korean Neurosurgical Society
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• v.46 no.1
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• pp.65-67
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• 2009

The authors report two cases of spontaneous regression of disc herniation at the level adjacent to the anterior lumbar interbody fusion (ALIF) level. This phenomenon may be due to the increased tension on the posterior longitudinal ligament (PLL) by appropriate restoration of the disc height and lumbar lordosis, which is a mechanism similar to ligamentotaxis applied to the thoracolumbar burst fracture.

• Journal of information and communication convergence engineering
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• v.8 no.2
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• pp.197-200
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• 2010

The FLL(frequency locked loop) circuit is used to generate an output signal that tracks an input reference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL is designed to allow the circuit to be fully integrated. In this paper, the temperature stable FLL circuit is designed by using full CMOS transistors. When the temperature is varied from $-20^{\circ}C$ to $70^{\circ}C$, the variation of output frequency is about from -2% to 1.6% from HSPICE simulation results.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2485-2488
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• 2003

본 논문에서는 DSP를 이용하여 운동하는 물체의 회전량을 측정하는 실린더형 진동 자이로스코프(이하 자이로) 제어기를 개발하였다. 진동 자이로를 구동하기 위해서는 정밀 진동제어와 신호 처리와 같은 고급 제어 기술이 필요하다. 정밀진동제어는 진동 자이로를 구동하기 위해 필요한 핵심기술로써 기존의 PLL(phase-locked loop)방식은 외부환경에 민감하여 구현이 까다로울 뿐만 아니라 자이로 개개의 고유 진동수가 다르기 때문에 대량 생산에 어려움이 있었다. 또한 자이로 출력 신호로부터 회전량을 검출하기 위해서는 진폭과 당향성 검출의 본 회로뿐만 아니라 잡음 제거와 신호 증폭, 온도 보상과 같은 전처리 과정도 필요하다. 본 논문에서는 DSP를 통해 정밀 진동제어와 잡음 제거, 방향성 검출 등의 기능들을 구현하였으며 증폭과 진폭(회전량) 검출은 아날로그 회로를 이용하였다. 또 한 외부와의 인터페이스를 위해 D/A 회로를 설계하였고 이들을 실험을 통해 검증하였다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.12
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• pp.31-39
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• 1993

In the playback signal processing of a digital magnetic recording system, the major signal processing processes consist of pulse equalization. pulse detection, clock recovery, and data recovery. Equalizer which compensates interference occurrde between pulses recorded in high density on a magnetic media is realized by pulse slimming method, and pulse detection by a integrating detector. Clock recovery from the detector output was accomplished by using PLL. and data recovery to reduce noise effects was carried out by utilizing the three sampling clocks recovered in clock recovery process. In this paper these processes are implemented in hardware and its performance is evaluated by experimenting with a commercial DAT. It was found that the playback signal processor proposed is suitable to the practical high density magnetic recording system.