• Title/Summary/Keyword: PLL

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Sensorelss Control of Single-Phase PM Motor drive and Restart Strategy (단상 모터에서 센서리스 제어와 재 시작 전략)

  • Park, Jaeyong;Ha, Jung-Ik
    • Proceedings of the KIPE Conference
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    • 2016.11a
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    • pp.99-100
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    • 2016
  • 본 논문에서는 위치 센서 없이 단상 모터를 운전하는 방법을 제안한다. 제안하는 센서리스 방식은 PM flux 추정기와 PLL 옵저버를 이용하여 구현된다. 이를 통해 홀 센서로 인한 조립상의 문제와 부피 증가 문제를 해결 할 수 있다. 또한 효율적인 운전을 위하여 0 속도가 아닌 파워가 다시 들어올 때 모터를 다시 구동하는 재 시작 전략 또한 제안한다. 이 방식은 위치 센서가 존재 하지 않기 때문에 재 시작시의 각도를 구하기 위한 0 전류 제어와 함께 전압의 zero crossing을 이용한다.

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COMPLETE AND INCOMPLETE FUZZY LOGIC CONTROLLERS

  • Teodorescu, H.N.;Brezulianu, A.
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1993.06a
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    • pp.1086-1089
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    • 1993
  • The paper deal with the differences between a fuzzy logic controller with a complete linguistic description and one with an incomplete linguistic description. The conditions to get a complete crisp controller by using a fuzzy logic controller with incomplete description are analyzed, and an application to the control of an analog PLL circuit is described, [1].

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Implementation of 234.7 MHz Mixed Mode Frequency Multiplication & Distribution ASIC (234.7 MHz 혼합형 주파수 체배 분배 ASIC의 구현)

  • 권광호;채상훈;정희범
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.11A
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    • pp.929-935
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    • 2003
  • An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

A Study on the Phase-looked Dielectric Resonator Oscillator using Bias Tuning (바이어스 동조를 이용한 위상 고정 유전체 공진 발진기에 관한 연구)

  • 류근관;이두한;홍의석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.10
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    • pp.1982-1990
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    • 1994
  • We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

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A Design and Construction of Phase-locked Dielectric Resonator Oscillator for VSAT (VSAT용 위상고정 유전체 공진 발진기의 설계 및 구현)

  • 류근관;이두한;홍의석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.10
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    • pp.1973-1981
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    • 1994
  • A PLDRO(Phase Locked Dielectric Resonator Oscillator) in Ku-band(10.95-11.70GHz) is designed with the concept of the feedback property of PLL(Phase Locked Loop). A series feedback type DRO is developed, and VCDRO(Voltage Controlled Dielectric Resonator Oscillator) using a varactor diode as a voltage-variable capacitor is implemented to tune oscillating frequency electrically. Then, PLDRO is designed by using a SPD(Sampling Phase Detector). This PLDRO is phase-locked voltage controlled DRO to reference source(VHF band) by SPD at 10.00 GHz for European FSS(Fixed Satellite Service). The PLDRO generates output power greater than 10dBm at 10.00 GHz and has phase noise of -80 dBc/Hz at 10 KHz offset from carrier. This PLDRO achieves much better frequency stability than conventional VCDRO.

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A Design of CMOS Transceiver for noncoherent UWB Communication system (비동기방식 UWB통신용 CMOS 아날로그 송수신단의 설계)

  • Park, Jung-Wan;Moon, Yong;Choi, Sung-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.71-78
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    • 2005
  • In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

The Performance Comparison of the CMA and MMA Algorithm for Blind Adaptive Equalization (블라인드 적응 등화를 위한 CMA와 MMA 알고리즘의 성능 비교)

  • Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.2
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    • pp.153-158
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    • 2012
  • This paper deals with the performance comparison of adaptive equalization algorithm, CMA and MMA, that is used for the minimization of the distortion and noise effect in the communication channel at receiver.. We confirmed the application possibilities of the point to point or point to multipoint digital transmission technologies by analyzing the performance of MMA which is changing the error function of CMA that is the possible algorithm of fast equalization by relatively simple arithmatic computation compared to the other method. In CMA algorithm, we need the PLL for the amplitude compensation only and not possible to phase compensation inherently. But in MMA algorithm, we confired that the amplitude and phase of received signal can be compensated by computer simulation. For the comparison of algorithm, we used the essential performance index, convergence characteristics and residual isi. The result of performance comparison of algorithms, the MMA has good in convergence characteristic and the CMA has good in residual isi that is used for the amplitude compensation.

A Simulation of Δ-Σ Modulators for Frequency Synthesizers of FMCW Radars (FMCW 레이더 주파수합성기용 델타-시그마 변조기의 시뮬레이션)

  • Hwang, In-Duk;Kim, Chang-Hwan
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.4
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    • pp.707-714
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    • 2012
  • After a single-stage, second-order, multiple-feedback ${\Delta}-{\Sigma}$ modulator and a two-stage, second-order MASH ${\Delta}-{\Sigma}$ modulator were analyzed and simulated using Simulink and Matlab and their characteristics were compared, the following result was obtained: 1) The two ${\Delta}-{\Sigma}$ modulators do not have group delay distortion. 2) The characteristics of the noise shaping are nearly identical. As a result of the noise shaping, the power spectral densities have slope of 40 dB/dec. 3) There was no spurious tone. 4) The input range of the two modulators is from -1 to +1 in common. 5) Because the output of the two-stage MASH modulator is 2-bits (4-levels), design of frequency dividers and charge pumps of PLL are more demanding.

Frequency Synchronization of Three-Phase Grid-Connected Inverters Controlled as Current Supplies

  • Fu, Zhenbin;Feng, Zhihua;Chen, Xi;Zheng, Xinxin;Yin, Jing
    • Journal of Power Electronics
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    • v.18 no.5
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    • pp.1347-1356
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    • 2018
  • In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from $-{\pi}$ to ${\pi}$. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.

Changes of Triglyceride Composition in Adlay Powder during Storage (율무가루 저장 중 Triglyceride 조성의 변화)

  • Han, Ji-Sook;Rhee, Sook-Hee;Cheigh, Hong-Sik
    • Korean Journal of Food Science and Technology
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    • v.23 no.1
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    • pp.102-108
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    • 1991
  • Raw adlay powder(RAP)was prepared and the changes of triglyceride composition in RAP lipid during storage at $35^{\circ}C$ for six months were studied. The RAP lipid consisted of 28 kinds of triglycerides and the major triglyceride in RAP lipid were those of OOL(24.14%), OLL(24.06%), OOO(12.58%), POL(9.01%), POO(8.87%), LLL(7.91%)and PLL(5.80%). During the storage at $35^{\circ}C$ for six months, the relative amounts of the triglyceride containing linoleic acid(OLL : 15.25%, LLL : 2.93%)considerably decreased, but those containing oleic acid(OOO : 23.77%. POO : 12.62%) increased. The triglycerides of LLA(0.44%)and PPLn(0.12%)disappeared during the storage.

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