• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1597-1602
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• 1999

An analog / digital mixed mode frequency multiplication and distribution ASIC for switch link or network synchronization of ATM switching system for B-ISDN has designed. This ASIC generates 234-7 MHz system clock and 77.76 MHz, 19.44 MHz user clocks using 46.94 MHz external clock. It also includes digital circuits for checking and selecting between the two external clocks. For effective ASIC design, full custom technique is used in analog PLL circuit and standard cell based technique is used in digital circuit. Resistors and capacitors are specially designed so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.816-824
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• 1999

Design and performance of 18 GHz phase locked dielectric resonator oscillator(PLDRO) for Point-to-point radio link using analog phase locked loop is described which achieve high stability and low SSB phase noise. The module consists of an 18 GHz voltage controlled dielectric resonator oscillator(VCDRO), buffered amplifier, analog phase detector which are integrated to form a miniature hybrid circuit. In addition, containing a low phase noise VHF PLL has been designed to lock any other conventional N times frequency of crystal oscillator. The module achieves stable phase locked state, exhibits output power of 21 dBm at 18.00 GHz, -34 dBc harmonic suppression and -75 dBc/Hz phase noise at 10 kHz offset frequency from carrier.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• The Journal of the Korea Contents Association
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• v.7 no.3
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• pp.42-49
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• 2007

This paper implements RFID(radio-frequency identification)System to which the system was apply SS(Spread Spectrum) method. The system designed by using the algorithm for microprocessor with PLL of the receiver, PN spread, modulation and demodulation of the transceiver, and transistor amplifier for the output of stabilized BPSK (Binary Phase Shift Keying) signal. furthermore, it reduced the interference of the signal by designing the micro-strip narrow banded patch antenna, which is convenient for printing and producing, and decreased the volume of filter size in the system. It is also designed for the lower powered system with the possible application to UHF band of $860\sim930MHz$ for the international standard frequency band, which is the quota share of RFID distribution system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.93-97
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• 2007

In this paper a new clock generation scheme for TDM-CDM converter in the Gap Filler for satellite DMB systems has been proposed. The scheme uses the frame sync signal from the Ku band TDM receiver to lock the VCXO which provides the system clock for the TDM-CDM converter. The locking algorithm can be easily implemented in the FPGA, so that no separate circuitry is needed as in conventional PLL. With a stable OCXO, The scheme can be used to generate the reference clock to the local oscillator for RF parts.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.854-857
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• 2015

As the number of devices integrated on system-on-chip(SoC) increases exponentially, energy reduction technology is essential. Dynamic Voltage and Frequency Scaling (DVFS) is a very effective technique for reducing power consumption. Since it requires complex voltage regulators and PLL circuits, DVFS tends to have significant overheads. In this paper, we propose a new voltage selection algorithm to minimize transition overhead for multiprocessor SoC (MPSoC). Simulation results show that proposed algorithm appears less energy consumption with transition overhead even though maintains performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.3
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.526-533
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• 2015

A new algorithm is proposed for the estimation of equivalent grid impedance at the point of common coupling of a grid-tie inverter output. The estimated impedance parameter can be used for the improvement of the performance and the stability of the distributed generation system. The estimation error is inevitable in the conventional estimation method because of the axis rotation due to PLL. In the conventional estimation error, the d-q voltage and current are used for the calculation of the impedance with active and reactive current injections. Conversely, in the proposed algorithm, the negative sequence current is injected, and then the negative sequence voltage is measured for the impedance estimation. As the positive and negative sequence current controller is independent and the PLL is based on the positive sequence component only, the estimation of the equivalent impedance can be achieved with high accuracy. Simulation and experimental results are compared to validate the proposed algorithm.