• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.194-200
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• 2003

In this paper, FSK(Frequency Shift Keying) demodulator which is widely used for FH-SS system is designed and the experimental results are analyzed. The performance of the ADPLL(All-digital Phase-Locked-Loop), which is the main part of the demodulator circuit, is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the ADPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. There is about 2${\mu}\textrm{s}$ difference in time constant of the PLL. This difference is not critical in the demodulator. And the experimental results show that the transmitted data is well demodulated when the phase difference between the FSK modulated signal and the reference signal is about 180 degree.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1375-1386
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• 2016

To decouple the secondary saliencies in sensorless permanent magnet synchronous machine (PMSM) drives, a repetitive control (RC) in the angle domain is proposed. In this paper, the inductance model of a concentrated windings surface-mounted PMSM (cwSPMSM) with strong secondary saliencies is developed. Due to the secondary saliencies, the estimated position contains harmonic disturbances that are periodic relative to the angular position. Through a transformation from the time domain to the angle domain, these varying frequency disturbances can be treated as constant periodic disturbances. The proposed angle-domain RC is plugged into an existing phase-locked loop (PLL) and utilizes the error of the PLL to generate signals to suppress these periodic disturbances. A stability analysis and parameter design guidelines of the RC are addressed in detail. Finally, the proposed method is carried out on a cwSPMSM drive test-bench. The effectiveness and accuracy are verified by experimental results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.2
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• pp.46-51
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• 2000

The generation of the intensive ultrasonic waves depend mainly on the energy conversion efficiency depending on high frequency oscillation of the generator and the control performance of stable output depending on load variation, respectively. In this dissertation, a new configuration of ultrasonic generator is specially proposed and designed for improving both efficiency and stability. The generating frequency is turned by a PLL. which is controlled through the detection on phase difference between outputs and currents of the loads and the output amplitude of MOSFET, Q1 are controlled by their products through the multiplier, which results in the control of the amplitude of voltage controlled oscillation. And finally, the proposed and designed ultrasonic generator is composed by the combination of the function in mentioned above. the analysis results of the proposed circuit shows a good agreement between simulations and experiments.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.25-30
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• 2014

This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.8
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• pp.88-95
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• 2006

This paper proposes an analog type Active Power Filter that adapts to the frequency change of a distributed power supply system. The proposed system removes the harmonic currents in the source power by injecting a compensation current that has the same frequency, 180 degree out of phase with the harmonic currents generated by the load. The detection of the harmonics in the source power for creating the compensating current is realized by a PLL(Phase Lock Loop) and a VCGIC(Voltage Controlled Generalized Impedance Converter). The operation of the proposed system is verified by simulation and experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1326-1331
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• 2001

This paper has been studied about design of a transceiver for data transmission. The transceiver has bandwidth of 424.7~424.95 MHz and uses half duplex communication method, PLL synthesized, 20 channel, 12.5 KHz channel bandwidth and FSK modulation/demodulation method. The transmission set is designed using low noise amplifier and power amplifier Also, it consists of low pass filter and resonation circuit for decrease of spurious signal. The receiver set is designed using dual conversion method. Finally, the transceiver set achieves the following characteristics 9.71dbm output power, 47dbc spurious property and $\pm$12.3 Jitter at sensitivity of -1134dbm.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.665-669
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• 2004

Generally, Slotless PM BLDC drive system is necessary that the three Hall-ICs evenly be distributed around the stator circumference and encoder be installed in case of the 3 phase motor. So, the Hall-ICs are set up in this motor to detect the main flux from the rotor, and the output signal from Hall-ICs is used to drive a power transistor to control the winding current. However, instead of using three Hall-ICs and encoder, we used only two Hall-ICs for the permanent magnet rotor position and for the speed feedback signals, and also for a microcontroller of 16-bit type (80C196KC) with the 3 phase Slotless PM BLDC whose six stator and two rotor designed. Two Hall-IC Hc and $H_B$ are placed on the endplate at 120 degree intervals, and with these elements, we can estimate information of the others phase in sequence through a rotating rotor.

• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.254-254
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• 2006

The sensitivity of plasmid DNA (pDNA) to S1 nuclease, an enzyme to cleave a single-strand DNA, was dramatically modulated through a supramolecular assembly (polyion complex micelle) with a synthetic block copolymer, poly(ethylene glycol)-b-poly(L-lysine) (PEG-PLL). The pDNA condensed in stoichiometric charge ratio was cleaved into 7 fragments each being 10/12, 9/12, 8/12, 6/12, 4/12, 3/12, and 2/12 of the original DNA length, on the other hand, the pDNA condensed in higher charge ratios (>4), were digested into non-specific manner. Condensation of the pDNA was investigated from two viewpoints that how does the rigid DNA molecules fold and condense and how does the condensation influence their biological activity.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.77-84
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• 2000

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.