• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.457-458
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• 2013

본 논문은 Simulink 모델을 기반으로 하여 FPGA 알고리즘을 설계하는 과정을 구현하였다. Simulink 모델은 SRF-PLL 제어기법을 적용하였으며, Simulink 모델은 기본적으로 부동소수점으로 구성된다. 그러나 FPGA 구현에 필요한 VHDL 코드는 고정 소수점 변환이 필요하므로, 부동 소수점 모델을 고정 소수점으로 변환하고 두 연산 기법의 시뮬레이션 결과를 비교분석하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.214-216
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• 2003

아날로그 NTSC 비디오 디코더 신호를 디코딩하여 디지털화된 컬러 값을 얻기 위해서는 컬러 버스트 신호를 동기화 해야 한다. 이 버스트 신호를 이용하여 Y. I. O의 값을 분리하기 때문이다. 아날로그 디코더의 경우에는 내부에 버스트 신호와 동기화 한 클럭을 PLL이나 DLL등을 이용하여 발생시켜서 I의 위치를 알아낸다. 비디오 신호 해독을 위한 전용의 PLL을 위해 아날로그 방식의 VLSI설계를 하는 것은 많은 노력이 들어갈 뿐만 아니라 특정 Fab에 종속되어 전체 칩의 이식성을 떨어뜨리게 된다. 본 논문에서는 아날로그 PLL이 없이도 디지털 입력데이터의 산술 연산을 통해서 컬러 버스트 동기화를 검출하는 방법을 제안한다.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.185-186
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• 2015

This paper introduces general single PLL(Phase Locked Loop) algorithm and compares with proposed PLL method. The suggested PLL uses low pass filter to reduce high harmonics in real grid and uses feed forward method to compensate phase delay of the low pass filter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2387-2394
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• 2013

A low spur phase-locked loop (PLL) with FVCO-sampled feedforward loop-filter has been proposed. Conventional PLL has loop filter made of a resistor and capacitors. The proposed PLL is working stably with the filter consisted of capacitors and a switch. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.45-53
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• 1996

In this paper, the convergence behavior of timing phase when an adaptive partial response equalizer and decision-directed type of a PLL work together in a digital recording channel is described. The phenomena of getting biased in timing phase when the convergence parameter of an adaptive partial response equalizer and timing recovery constant of a PLL are not selected properly is introduced. The phenomena, occurring due to perturbation of timing phase, are analyzed, by computer simulation and the region of ocnvergence for timing phase is discussed. Also, a method to overcome the phenomena using a variable step-size parameter is described.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.277-280
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• 2005

In this paper, we propose a frequency synthesizer for dualband repeater. The dual-band RF technology for applications to the wireless repeater for CDMA and WCDMA mobile communications has been developed in this paper. The dualband PLL module consisted of dual-band VCO and one PLL IC has been developed. The main technological efforts for the dual-band PLL module is to suppress the intermodulation distortion by applying the miniature ceramic filter using the slow wave characteristics. The dual-band miniature RF module including dual-band PLL module and one MCU controller is very attractive for applications to the miniature dual-band RF mobile repeaters.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.845-848
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• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.865-870
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• 2001

In this paper, we analyse the effect of phase noise from PLL frequency synthesizer on 64 QAM when detecting corrupted signals. To predict the phase noise of an oscillator very accurately, we assume that the oscillator is linearly time-varying when the input impulsive current to the oscillator is small. The performance of the detector which detects the corrupted signal by oscillator phase noise is compared with that when the detector is only affected by AWGN and then analyse how much the phase noise degrades the system performance for 64 QAM.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.284-288
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• 2005

This paper proposes the direct detection method of phase angle for the power source, which is based on the PLL method. The proposed method using a bidirectional photo-coupler is used to directly detect the zero crossing of phase voltage and calculate the angular frequency in the controller based on a M/T algorithm. Through the method, the additional installation space in the traditional method using a potential transformer can be minimized and it can be easy to design. The paper presents straightforward schematic circuits, design and experimental results.