• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1097-1100
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• 1998

In this paper, the PLL(Phase-Locked Loops) for low voltage and high speed operation is described. In other to obtaining above objects, new CMOS circuit technologies have been used in the each block circuit of PLL. It operates with a lock range from 110 up to 700 MHz and has a peak to peak jitter of 50 ps at operating frequency of 250 MHz. It was fabricated in a $0.6\mu\textrm{m}$ CMOS technology and dissipated 45 mW from a single 3.3V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1289-1301
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• 1997

In a SDH network, one of the most important issues is the realization of network synchronization. In this paper, we presented the relationship between parameters and control algorithm of DP-PLL for design in a SDH based time, SSM processing time, PJE counter and reference switching time, and analyzed phase transients for one node and mutiple nodes through our simulation results with a standard specification. We suggested suitable design method of SDH-DP-PLL.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.87-88
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• 2014

The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.240-242
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• 2008

본 논문에서는 단상 PLL알고리즘 중 하나인 영점검출 방식에서의 순시제어 불능을 극복하기 위해 arcsin을 이용한 알고리즘을 제안하였다. 또한 시뮬레이션을 통해 영점검출과 비교하여 제안된 PLL알고리즘의 순시제어 가능성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.162-163
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• 2012

계통연계 인버터에서 계통전압과 위상을 일치시키기 위한 PLL은 필수이다. 기존의 PLL의 경우 계통전압에 불평형이 발생하면 계통의 위상을 정확하게 추종할 수 없기 때문에 제어를 할 수 없게 되고 이는 시스템에 심각한 영향을 미칠 수 있다. 따라서 불평형 전압이 발생하여도 정확하게 위상을 추종할 수 있는 기법의 필요하다. 본 논문에서는 SOGI(Second - Order Generalized Intergrator)를 소개하고 시뮬레이션과 실험을 통해 그 타당성을 검증한다.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.41 no.6
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• pp.678-684
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• 1996

Seed pelleting have successfully been used in many crops for better crop estab-lishment and for mechanizing seeding process for small crop seeds in developed countries. In this experiment various pelleting materials and binders were tested to get basic information on the shape, hardness and germination of pelleted seesds of cabbage (cv. Seoul Beachoo) and rice (cv: Ilpoom). PLL-11, paper clay, lime and coal ash were good materials to make smooth shape of the pellets with pel gel and AG-11 as binders, and PLL-ll as material and pelgel and AG-11 as binders were the best among them in consideration of shape and hardness together. The hardness of the pelleted seeds were differed with each other depending on both of the pelleting materials and binders. Pelleted cabbage seeds coated by pelgel as binder with different materials showed lower germination percentge than control in general, but the seeds pelleted by PLL-11 with different binders showed no restraint effects. When the cabbage seed pelleted by PLL-11 with pelgel as binder showed almost same germination percentage as control. The pH and electrical conductivity of the extract from bentonite and zeolite were very higher than other materials tested and germination percentage showed a little lower than control when the cab-bage seed planted on the filter paper damped with the extract. As a result, PLL-11 as pelleting material and pel gel and AG-11 as binder appeared the good materials to make pellets of cabbage seeds and rice in consideration of shape, hardness and germination.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.835-842
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• 2004

In this paper, we have analyzed the MC-DS/CDMA system with input signal synchronized completely through adjustment of the gain in the PLL loop, by using the hybrid SC/MRC-(2/3) technique, which is said to one of the optimal diversity techniques under the multi-path fading environment, assuming that phase error is defined to the phase difference between the received signal from the multi-path and the reference signal in the PLL of the receiver. Also, assuming that the regarded radio channel model for the mobile communication is subject to the Nakagami-m fading channel, we have developed the expressions and performed the simulation under the consideration of various factor, in the MC/DS-CDMA system with the hybrid SC.MRC-(2/3) diversity method, such as the Nakagami fading index(m), $the\;number\;of\;paths\;(L_p),$ the number of hybrid SC.MRC-(2/3) $diversity\;branches\;(L,\;L_c),$ the number of users (K), the number of subcarriers (U), and the gain in the PLL loop. As a result of the simulation, it has been confirmed that the performance improvement of the system can be achieved by adjusting properly the PLL loop in order for the MC/DS-CDMA system with the hybrid SC/MRC-(2/3) diversity method to receive a fully synchronized signal. And the value of the gain in the PLL loop should exceed 7dB in order for the system to receive the signal with prefect synchronization, even though there might be a slight difference according to the values of the fading index and the spread processing gain of the subcarrier.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of Korean Neurosurgical Society
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• v.61 no.1
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• pp.89-96
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• 2018

Objective : Morphometric data for the lumbar posterior longitudinal ligament (PLL) was investigated to identify whether there is a difference in the morphometry of the PLL of the lumbar spine at each level with respect to the pattern of intervertebral disc displacement. Methods : In 14 formalin-fixed adult cadavers (12 males and 2 females), from L1 to L5, the authors measured the width and height of the PLL and compared them with other landmarks such as the disc and the pedicle. Results : Horizontally, at the upper margin of the disc, the central portion of the superficial PLL covered 17.8-36.9% of the disc width and the fan-like portion of the PLL covered 63.9-76.7% of the disc width. At the level of the median portion of the disc, the PLL covered 69.1-74.5% of the disc width. Vertically, at the level of the medial margin of the pedicle, the fan-like portion of the PLL covered 23.5-29.9% of the disc height. In general, a significant difference in length was not found in the right-left and male-female comparisons. Conclusion : This study presents the morphometric data on the pattern of intervertebral disc displacement and helps to improve the knowledge of the surgical anatomy of the lumbar PLL.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2326-2332
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.