• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.1
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• pp.29-33
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• 2010

As the demands for the higher data transmission speed and capacity as well as integration density grow throughout the network, much works have being done in order to integrate the Electrical PCB with Optical PCB. However, one of the most troublesome problems in the commercial bonding process is to need the high temperature for the bonding. Due to the high temperature bonding process, lots of side problems are followed such as warpage and crack, etc. In this paper, we tried to develop the new bonding technology with low temperature around $100^{\circ}C$. As a result of this study, the PCB bonding technology with high bonding strength is demonstrated with the value of bonding strength from 7 to 8 MPa at the temperature of $100^{\circ}C$.

• 한국금형공학회:학술대회논문집
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• 2008.06a
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• pp.209-213
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• 2008

In this work, we have proposed a method for calculating the residual stress developed during the PCB thermo-compression bonding precess. Residual stress is the most important factor that causes PCB warpage in accordance with the pattern design. In this work, a single-layed double-sided PCB, which is comprised of the dielectric (FR-4) substrate in the middle and copper cladding on the both top and bottom sides, is considered. A reference temperature, where all stress is free, is calculated by comparing the calculated and measured warapge of a PCB of which copper cladding of the top side is removed. Then, the reesidual stress values is calculated for the double-sided PCB.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.12
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• pp.84-91
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• 2010

The bonding process of LCD panel is attaching an inner lead to an outer lead in the production line of LCD panel module. It is composed of an OLB process and a PCB bonding process. Since bonding tool assembly is one of the core parts of the bonding equipment that determines the durability and performance of the final product, much design efforts to enhance uniformity and efficiency of the process have been made. In this paper, FE analyses have been employed to determine the bonding tool size. Bonding tool of long bar shape has been simplified as a piece with same heater pitch, and appropriate boundary conditions such as convection and radiation are considered. Thermal analysis results by the FEM have been validated by the experiments. With the use of FE analysis varies design parameters and the corresponding effects have been evaluated. It was observed that the approach presented in this paper could be employed for the design of LCD module bonding tool.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.12
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• pp.92-98
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• 2010

The design of press bonding tool in LCD module equipment is a very complex and difficult task because many design able variables are involved while their effects are not known. It takes longtime experiments and much expenses to verify the effects of these design variables. However the optimization of bonding tool using OLB(outer lead bonding) and PCB Bonding is a very important problem in LCD manufacturing process, so much design efforts have been made for improving the bonding tool performance. In this paper, a reasonable and fast process which gives optimized solution under the design requirements has been presented. Both analytical and statistical methods are employed in this process. A reliable analytic model using experiment-oriented FE analysis can be obtained, in which the regression equations that predict the tool efficiency from various DOE method are found. Improvement of tool efficiency could be estimated by the regression equations using meaningful factors converged by RSM(Response Surface Method). With this process a reasonable optimized solution that meets a variety of design requirements can be easily obtained.

• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.49-54
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• 1993

This paper discusses the reliability of solder joints of electronic devices on printed circuit board. Solder application is usually done by screen printing method for the bonding between outer leads of devices and thick film(Ag/Pd) pattern on Hybrid IC as wel1 as Cu lands on PCB. As result of thermal stresses generated at the solder joints due to the differences of thermal expansion coefficients between packge body and PCB, Micro cracking often occurs due to thermal fatigue failure at solder joints. The initiation and the propagate of solder joint crack depends on the environmental conditions, such as storage temperature and thermal cycling. The principal mechanisms of the cracking pheno- mana are the formation of kirkendal void caused by the differences in diffusion rate of materials, ant the thermal fatigue effect due to the differences of thermal expansion coefficient between package body and PCB. Finally, This paper experimentally shows a way to supress solder joints cracks by using low-${\alpha}$ PCB and the packages with thin lead frame, and investigates the phenomena of diffusion near the bonding interfaces.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.597-598
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• 2006

This paper describes a development of a new $1.4{\times}1.1$ and $2.0{\times}1.4mm$ RF SAW filters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• Proceedings of the KWS Conference
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• 2006.10a
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• pp.172-174
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• 2006