• Title/Summary/Keyword: Oxide thin film transistors

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Characterization of thin film transistors using hydrogenated ZnO films and effects of thermal annealing (수소화된 산화아연을 이용한 박막 트랜지스터의 제작 및 열처리 효과)

  • Lee, Sang-Hyuk;Kim, Won;Uhm, Hyun-Seok;Park, Jin-Seok
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.1412-1413
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    • 2011
  • Effects of thermal annealing on electrical characteristics of thin film transistors (TFTs) using hydrogenated zinc oxide (ZnO:H) films as active channel were extensively investigated. The ZnO:H films were deposited at room temperature by RF sputtering. The device parameters of the ZnO:H-based TFTs, such as threshold voltage ($V_{th}$), subthreshold swing (S.S.), and on-off current ratio ($I_{on}/I_{off}$), were characterized in terms of the annealing temperature as well as the gas flow ratio of $H_2$/Ar.

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Dependence of Self-heating Effect on Width/Length Dimension in p-type Polycrystalline Silicon Thin Film Transistors

  • Lee, Seok-Woo;Kim, Young-Joo;Park, Soo-Jeong;Kang, Ho-Chul;Kim, Chang-Yeon;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.505-508
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    • 2006
  • Self-heating induced device degradation and its width/length (W/L) dimension dependence were studied in p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs). Negative channel conductance was observed under high power region of output curve, which was mainly caused by hole trapping into gate oxide and also by trap state generation by self-heating effect. Self-heating effect became aggravated as W/L ratio was increased, which was understood by the differences in heat dissipation capability. By reducing applied power density normalized to TFT area, self-heating induced degradation could be reduced.

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Influence of Channel Thickness Variation on Temperature and Bias Induced Stress Instability of Amorphous SiInZnO Thin Film Transistors

  • Lee, Byeong Hyeon;Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.1
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    • pp.51-54
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    • 2017
  • TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

Routes to Improving Performance of Solution-Processed Organic Thin Film Transistors

  • Li, Flora M.;Hsieh, Gen-Wen;Nathan, Arokia;Beecher, Paul;Wu, Yiliang;Ong, Beng S.;Milne, William I.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.1051-1054
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    • 2009
  • This paper investigates approaches for improving effective mobility of organic thin film transistors (OTFTs). We consider gate dielectric optimization, whereby we demonstrated >2x increase in mobility by using a silicon-rich silicon nitride ($SiN_x$) gate dielectric for polythiophene-based (PQT) OTFTs. We also engineer the dielectric-semiconductor ($SiN_x$-PQT) interface to attain a 27x increase in mobility (up to 0.22 $cm^2$/V-s) using an optimized combination of oxygen plasma and OTS SAM treatments. Augmentative material systems by combining 1-D nanomaterials (e.g., carbon nanotubes, zinc oxide nanowires) in an organic matrix for nanocomposite OTFTs provided a further boost in device performance.

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Stability enhancement of armorphous znic oxide thin film transistors fabricated by pulsed laser deposition with DBD (PLD-DBD 공정으로 제작된 비정질 Zn 산화물 박막트랜지스터의 안정성 향상)

  • Chun, Yoon-Soo;Chong, Eu-Gene;Jo, Kyoung-Chol;Kim, Seung-Han;Jung, Da-Woon;Lee, Sang-Yeol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.391-391
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    • 2010
  • The stability enhancement of Znic oxide thin film transistor deposited by PLD-DBD has been reported here using the bias temperature stress test. Znic oxide (ZnO) thin films were deposited on $SiO_2$/Si (100) by pulsed laser deposition method with and without dielectric barrier discharge (DBD) method. The DBD is the efficient method to adopt the nitrogen ions into the thin films. The TFT characteristics of ZnO TFTs with and without Nirogen (N) doping show similar results with $I_{on/off}$ of $10^5{\sim}10^6$. However. the bias temperature stress (BTS) test of N-doped ZnO TFT with DBD shows higher stability than that of ZnO TFT.

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Effect of Subthreshold Slope on the Voltage Gain of Enhancement Mode Thin Film Transistors Fabricated Using Amorphous SiInZnO

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.5
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    • pp.250-252
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    • 2017
  • High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

Annealing effects on the characteristics of Sputtered ZnO films for ZnO-based thin-film transistors

  • Park, Yong-Seob;Kim, Han-Ki
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.08a
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    • pp.112-112
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    • 2010
  • Zinc Oxide (ZnO) thin-films were deposited according to the magnetron sputtering method. The deposited ZnO films were annealed with RTA equipment at various annealing temperatures in an vacuum ambient. The influence of the annealing temperature on the structural, electrical, and optical properties of the ZnO films was experimentally investigated, and the effect of conductivity of the ZnO active layer on the device performance of the oxide-TFT was tested. As a result, an increase of the annealing temperature was attributed to improvements of crystallinity in ZnO films. The grain size was found to lead to an increase of conductivity in the ZnO films. Fabricated ZnO TFTs with annealed ZnO active layer provided good performance in the TFT devices. Consequently, the performance of the TFT was determined by the conductivity of the ZnO film, which was related to the structural properties of the ZnO film.

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Improved Electrical Properties of Indium Gallium Zinc Oxide Thin-film Transistors by AZO/Ag/AZO Multilayer Transparent Electrode

  • No, Yeong-Su;Yang, Jeong-Do;Park, Dong-Hui;Wi, Chang-Hwan;Jo, Se-Hui;Kim, Tae-Hwan;Choe, Won-Guk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.443-443
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    • 2012
  • We fabricated a-IGZO TFT with AZO/Ag/AZO transparent multilayer source/drain contacts by rf magnetron sputtering. Enhanced electrical device performance of a-IGZO TFT with AZO/Ag/AZO multilayer S/D electrodes (W/L = = 400/50 mm) was achieved with a subs-threshold swing of 3.78 V/dec, a minimum off-current of 10-12 A, a threshold voltage of 1.80 V, a field effect mobility of 10.86 cm2/Vs, and an on/off ration of 9x109. It demonstrated the potential application of the AZO/Ag/AZO film as a promising S/D contact material for the fabrication of the high performance TFTs.

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Investigation on Contact Resistance of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors with Various Electrodes by Transmission Line Method

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.3
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    • pp.139-141
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    • 2015
  • Contact resistance of interface between the channel layers and various S/D electrodes was investigated by transmission line method. Different electrodes such as Ti/Au, a-IZO, and multilayer of a-IGZO/Ag/a-IGZO were compared in terms of contact resistance, using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes showed good performance and low contact resistance due to the homo-junction with channel layer.

High stable oxide thin-film transistors

  • Jeong, U-Seok;Sin, Jae-Heon;Yun, Seong-Min;Yang, Sin-Hyeok;Jeong, Seung-Muk;Yu, Min-Gi;Byeon, Chun-Won;Hwang, Chi-Seon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2008.08a
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    • pp.89-89
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    • 2008
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