• 한국전기전자재료학회논문지
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• 제17권4호
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.284-284
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• 2011

Recently, the increasing degree of device integration in the fabrication of Si semiconductor devices, etching processes of nano-scale materials and high aspect-ratio (HAR) structures become more important. Due to this reason, etch selectivity control during etching of HAR contact holes and trenches is very important. In this study, The etch selectivity and etch rate of TEOS oxide layer using ACL (amorphous carbon layer) mask are investigated various process parameters in CH2F2/C4F8/O2/Ar plasma during etching TEOS oxide layer using ArF/BARC/SiOx/ACL multilevel resist (MLR) structures. The deformation and etch characteristics of TEOS oxide layer using ACL hard mask was investigated in a dual-frequency superimposed capacitively coupled plasma (DFS-CCP) etcher by different fHF/ fLF combinations by varying the CH2F2/ C4F8 gas flow ratio plasmas. The etch characteristics were measured by on scanning electron microscopy (SEM) And X-ray photoelectron spectroscopy (XPS) analyses and Fourier transform infrared spectroscopy (FT-IR). A process window for very high selective etching of TEOS oxide using ACL mask could be determined by controlling the process parameters and in turn degree of polymerization. Mechanisms for high etch selectivity will discussed in detail.

• 한국전기전자재료학회논문지
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• 제15권1호
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• pp.7-14
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• 2002

In this paper, neutral networks are used to build models of oxide film etched In CHF$_3$/CF$_4$ with a magnetically enhanced reactive ion etcher(MERIE). A statistical 2$\^$4-1/ experimental design plus one center point was used to characterize relationships between process factors and etch responses. The factors that were varied include radio frequence(rf) power, pressure, CHF$_3$ and CF$_4$ flow rates. Resultant 9 experiments were used to train neural networks and trained networks were subsequently tested on its appropriateness using additionally conducted 8 experiments. A total of 17 experiments were thus conducted for this modeling. The etch responses modeled are dc bias voltage, etch rate and etch uniformity A qualitative, good agreement was obtained between predicted and observed behaviors.

• 한국세라믹학회지
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• 제31권5호
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• pp.485-490
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• 1994

The reactive ion etching characteristics of aluminum oxide films, prepared by PECVD, were investigated in the CCl4 plasma. The atomic chlorine concentration and the DC self bias were determined at various etching conditions, and their effects on the etch rate of aluminum oxide film were studied. The bombarding energy of incident particles was found to play the more important role in determining the etch rate of aluminum oxide rather than the atomic chlorine concentration. It is considered to be because the bombardment of ions or neutral atoms breaks the strong Al-O bonds of aluminum oxide to help activate the formation reaction of AlCl3 which is the volatile etch product.

• 대한전자공학회논문지SD
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• 제41권8호
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• pp.31-36
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• 2004

본 논문에서는 UV 처리와 BOE 세정을 이용하여 레이저 어닐링 전의 실리콘 표면에 자연 산화막을 제거하여 다결정 실리콘 TFT의 신뢰성을 향상시키는 방법을 제안하였다. 전처리 공정이 다결정 실리콘의 표면 거칠기에 미치는 영향을 AFM으로 측정하였으며, 다결정 실리콘 TFT의 전기적 특성인 스위칭 특성과 항복특성을 대형 유리기판의 위치와 전처리의 유무에 대해서 조사하였다.

• 한국전기전자재료학회논문지
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• 제14권1호
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Progress in Superconductivity
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• 제12권2호
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• pp.114-117
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• 2011

We report our efforts on the development of Nb-based non-hysteretic Josephson junction fabrication process for quantu device applications. By adopting and modifying the existing Nb-aluminum oxide tunnel junction process, we develop a process for non-hysteretic Josephson junction circuits using metal-silicide as metallic barrier material. We use sputter deposition of Nb and $MoSi_2$, PECVD deposition of silicon oxide as insulator material, and ICP-RIE for metal and oxide etch. The advantage of the metal-silicide barrier in the Nb junction process is that it can be etched in $SF_6$ RIE together with Nb electrode. In order to define a junction area precisely and uniformly, end-point detection for the RIE process is critical. In this paper, we employed thin Al layer for the etch stop, and optimized the etch condition. We have successfully demonstrated that the etch stop properties of the inserted Al layer give a uniform etch profile and a precise thickness control of the base electrode in Nb trilayer junctions.

• Journal of information and communication convergence engineering
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• 제1권2호
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• pp.67-69
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• 2003

The experimental studies for the etch properties of the oxide grown on silicon substrate, which is in diluted hydrogen fluoride (HF) solution, are presented. Using different ion implantation dosages, dopants and energies, silicon substrate was implanted. The wet etching in diluted HF solution is used as a mean of wafer cleaning at various steps of VLSI processing. It is shown that the wet etch rate of oxide grown on various implanted silicon substrates is a strong function of ion implantation dopants, dosages and energies. This phenomenon has never been reported before. This paper shows that the difference of wet etch rate of oxide by ion implantation conditions is attributed to the kinds and volumes of dopants which was diffused out into $SiO_2$ from implanted silicon during thermal oxidation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.363-363
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• 2010

After oxide wet etch with BOE(Buffered Oxide Etchant), triangle type defect maps were inspected and SEM image showed them unetch of oxide layer. As decreasing design rule, oxide unetch has become a crucial issue and has affected the yield and quality.

• 한국진공학회지
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• 제5권1호
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• pp.6-13
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• 1996

The kinetics of native oxide formation on the (Al, Ga)As and (Cd, Mn)Te have been studied by X-ray photoelectron spectroscopy(XPS) and Auger electron spectroscopy(AES). The regrowth of native oxide after 3keV Ar ion sputter etch and deionized water etch has been studied. The previous report exhibited that the native oxide on CdTe and GaAs can be removed completely by deionzied(DI) water only[1]. On the other hand, the airgrown native oxide on (Al, Ga)As become nonhomogeneous and the regrown native oxide on (Cd,Mn)Te can be partially removed.