• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.66-66
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• 1999

최근 들어 다결정 SiGe은 MOS(Metal-Oxide-Semiconductor)에서 기존에 사용되던 다결정 Si 공정과의 호환성 및 여러 장점으로 인하여 다결정 Si 대안으로 많은 연구가 진행되고 있다. 고농도로 도핑된 P type의 다결정 SiGe은 Ge의 함량에 따른 일함수의 조절과 낮은 비저항으로 submicrometer CMOS 공정에서 게이트 전극으로 이용하려는 연구가 진행되고 있으며, 55$0^{\circ}C$ 이하의 낮은 온도에서도 증착이 가능하고, 도펀트의 활성화도가 높아서 TFT(Thin Film Transistor)에서도 유용한 재료로 검토되고 있다. 현재까지 다결정 SiGe의 증착은 MBE, APCVD, RECVD. HV/LPCVD 등 다양한 방법으로 이루어지고 있다. 이중 HV/LPCVD 방법을 이용한 증착은 반도체 공정에서 게이트 전극, 유전체, 금속화 공정 등 다양한 공정에서 사용되고 있는 방법으로 현재 사용되고 있는 반도체 공정과의 호환성의 장점으로 다결정 SiGe 게이트 전극의 증착 공정에 적합하다고 할 수 있다. 본 연구에서는 HV/LPCVD 방법을 이용하여 게이트 전극으로의 활용을 위한 다결정 SiGe의 증착 메카니즘을 분석하고 Ex-situ implantation 후 열처리에 따라 나타나는 활성화 정도를 분석하였다. 도펀트를 첨가하지 않은 다결정 SiGe을 주성엔지니어링의 EUREKA 2000 장비를 이용하여, 1000$\AA$의 열산화막이 덮혀있는 8 in 웨이퍼에 증착하였다. 증착 온도는 55$0^{\circ}C$에서 6$25^{\circ}C$까지 변화를 주었으며, 증착압력은 1mtorr-4mtorr로 유지하였다. 낮은 증착압력으로 인한 증착속도의 감소를 방지하기 위하여 Si source로서 Si2H6를 사용하였으며, Ge의 Source는 수소로 희석된 10% GeH4와 100% GeH4를 사용하였다. 증착된 다결정 SiGe의 Ge 함량은 RBS, XPS로 분석하였으며, 증착된 박막의 두께는 Nanospec과 SEM으로 관찰하였다. 또한 Ge 함량 변화에 따른 morphology 관찰과 변화 관찰을 위하여 AFM, SEM, XRD를 이용하였으며, 이온주입후 열처리 온도에 따른 활성화 정도의 관찰을 위하여 4-point probe와 Hall measurement를 이용하였다. 증착된 다결정 SiGe의 두게를 nanospec과 SEM으로 분석한 결과 Gem이 함량이 적을 때는 높은 온도에서의 증착이 더 빠른 증착속도를 나타내었지만, Ge의 함량이 30% 되었을 때는 온도에 관계없이 일정한 것으로 나타났다. XRD 분석을 한 결과 Peak의 위치가 순수한 Si과 순수한 Ge 사이에 존재하는 것으로 나타났으며, ge 함량이 많아짐에 따라 순수한 Ge쪽으로 옮겨가는 경향을 보였다. SEM, ASFM으로 증착한 다결정 SiGe의 morphology 관찰결과 Ge 함량이 높은 박막의 입계가 다결정 Si의 입계에 비해 훨씬 큰 것으로 나타났으며 근 값도 증가하는 것으로 나타났다.

• Journal of the Korean Ceramic Society
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• v.47 no.4
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• pp.329-332
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• 2010

In order to investigate the effect of tail state on the electrical and the optical properties in amorphous IGZO(a-IGZO), a-IGZO films were deposited at room temperature on fused silica substrats using pulsed laser deposition method. The laser pulse energy was used as the processing parameter. In-situ post annealing was carried out at $150^{\circ}C$ right after the film deposition. The $O_2$ partial pressure during the deposition and the post annealing was fixed to 10mTorr. The carrier mobility of the a-IGZO films had a range from 2 to $18\;cm^2/Vs$ at carrier concentrations greater than $10^{18}\;cm^{-3}$. As the laser energy density increased, the Hall mobility increased. And post annealing improved the Hall mobility, as well. The optical property was examined using the ultraviolet-visible spectroscopy. The a-IGZO films that have low Hall mobility exhibited stronger and broader absorption tails in >3.0 eV region. Post annealing reduced the intensity of the tail-like absorption. The absorption tail in a-IGZO films is an important factor which affects the electrical and the optical properties.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.873-879
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• 2007

We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the $2^{nd}\;and\;3^{rd}$ harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.665-670
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• 2016

In this paper, we suggest the design of OP-AMP using MOSFET in the operation of sub-threshold condition as a basic unit of an IoT. The sub-threshold operation of MOSFET is useful for an ultra low power consumption of sensor network system in the IoT, because it cause the supply voltage to be reduced. From the simulation result using 0.35 um CMOS process, the supply voltage, VDD can be reduced with 0.6 V, open-loop gain of 43 dB and the power consumption was evaluated with about $1.3{\mu}W$ and the active size for an integration was measured with $64{\mu}m{\times}105{\mu}m$. It is expected that the proposed circuit is applied to the low power sensor network for IoT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.1
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• pp.54-58
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• 2017

The effect of low temperature ($250^{\circ}C$) heat treatment after electron irradiation (irradiation time = 30, 180, 300s) on the chemical bonding and electrical properties of ZnO thin films prepared using a sol-gel process were examined. XPS (X-ray photoelectron spectroscopy) analysis showed that the electron beam irradiation decreased the concentration of M-O bonding and increased the OH bonding. As a result of the electron beam irradiation, the carrier concentration of ZnO films increased. The on/off ratio was maintained at ${\sim}10^5$ and the $V_{TH}$ values shifted negatively from 11 to 1 V. As the irradiation time increased from 0 to 300s, the calculated S. S. (subthreshold swing) of ZnO TFTs increased from 1.03 to 3.69 V/decade. These values are superior when compared the sample heat-treated at $400^{\circ}C$ representing on/off ratio of ${\sim}10^2$ and S. S. value of 10.40 V/decade.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.407-407
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• 2014

Nanotechnology, especially vertically grown silicon nanowires, has gotten great attentions in biology due to characteristics of one dimensional nanostructure; controllable synthetic structure such as lengths, diameters, densities. Silicon nanowires are promising materials as nanoelectrodes due to their highly complementary metal-oxide-semiconductor (CMOS) - and bio-compatibility. Silicon nanowires are so intoxicated that are effective for bio molecular delivery and electrical stimulation. Vertical nanowires with integrated Au tips were fabricated for electrical intracellular interfacing with PC-12 cells. We have made synthesized two types of nanowire devices; one is multi-nanowires electrode for bio molecular sensing and electrical stimulation, and the other is single-nanowires electrode respectively. Here, we demonstrate that differentiation of Nerve Growth Factor (NGF) treated PC-12 cells can be promoted depending on different magnitudes of electrical stimulation and density of Si NWs. It was fabricated by both bottom-up and top-down approaches using low pressure chemical vapor deposition (LPCVD) with high vacuuming environment to electrically stimulate PC-12 cells. The effects of electrical stimulation with NGF on the morphological differentiation are observed by Scanning Electron Microscopy (SEM), and it induces neural outgrowth. Moreover, the cell cytosol can be dyed selectively depending on the degree of differentiation along with fluorescence microscopy measurement. Vertically grown silicon nanowires have further expected advantages in case of single nanowire fabrication, and will be able to expand its characteristics to diverse applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.358-358
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• 2014

인간과 기기간의 상호작용 심화에 의하여 모든 기기의 지능화, 첨단화 등이 요구됨에 따라 정보 기술 및 디스플레이 기술의 개발이 활발히 이루어지고 있는 가운데 투명 전자 소자에 대한 연구가 급증하고 있다. 산화물 반도체는 가시광 영역에서 투명하고, 비정질 반도체에 비하여 이동도가 100 배 이상 크고, 결정화 공정을 거친 폴리 실리콘과 비슷한 값을 가지거나 조금 낮으며 유연한 소자에도 쉽게 적용이 가능하다는 장점을 가지고 있어 투명 전자 소자 제작시에 주로 이용되는 물질이다. 대부분의 산화물 반도체 박막 증착 방법은 스퍼터링 방법이나 유기금속 화학증착법과 같은 방법으로 막을 형성하는데 이러한 증착 방법들은 고품질의 박막을 성장시킬 수 있다는 장점이 있으나 고가의 진공장비 및 부대 시설이 이용되고 이로 인한 제조비용의 상승이 되고, 기판 선택에 제약이 있는 단점이 있다. 따라서, 이러한 문제점을 개선하기 위하여 고가의 진공 장비가 필요 없이 스핀 코팅 방법이나 딥핑 방법 등에 의하여 공정 단계의 간소화, 높은 균일성, 기판 종류에 상관없는 소자의 대면적화가 가능한 용액 공정 기술이 각광을 받고 있다. 그러나 용액 공정 기반의 박막을 형성하기 위해서는 비교적 높은 공정온도 혹은 압력 등의 외부 에너지를 필요로 하므로 열에 약한 유리 기판이나 유연한 기판에 적용하기가 어렵다. 최근 이러한 문제점을 해결하기 위하여 높은 온도의 열처리(thermal annealing) 를 대신 할 수 있는 microwave irradiation (MWI)에 대한 연구가 보고되고 있다. MWI는 $100^{\circ}C$ 이하에서의 저온 공정이 가능하여 높은 공정 온도에 대한 문제점을 해결할 뿐만 아니라 열처리 방향을 선택적으로 할 수 있다는 장점을 가지고 있어 현재 투명 디스플레이 분야에서 주로 이용되고 있다. 따라서 본 연구에서는 HfOx 기반의 metal-oxide-semiconductor (MOS) capacitor를 제작하여 MWI에 따른 전기적 특성을 평가하였다. MWI는 금속의 증착 전과 후, 그리고 시간에 따른 조건을 적용하였으며 최적화된 조건의 MWI은 일반적인 퍼니스 장비에서의 높은 온도 열처리에 준하는 우수한 전기적 특성을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.95-95
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• 2014

An OLED(Organic Light-Emitting Diode) device based on the emissive electroluminescent layer a film of organic materials. OLED is used for many electronic devices such as TV, mobile phones, handheld games consoles. ULVAC's mass production systems are indispensable to the manufacturing of OLED device. ULVAC is a manufacturer and worldwide supplier of equipment and vacuum systems for the OLED, LCD, Semiconductor, Electronics, Optical device and related high technology industries. The SMD Series are single-substrate sputtering systems for deposition of films such as metal films and TCO (Transparent Conductive Oxide) films. ULVAC has delivered a large number of these systems not only Organic Evaporating systems but also LTPS CVD systems. The most important technology of thin-film encapsulation (TFE) is preventing moisture($H_2O$) and oxygen permeation into flexible OLED devices. As a polymer substrate does not offer the same barrier performance as glass substrate, the TFE should be developed on both the bottom and top side of the device layers for sufficient lifetimes. This report provides a review of promising thin-film barrier technologies as well as the WVTR(Water Vapor Transmission Rate) properties. Multilayer thin-film deposition technology of organic and inorganic layer is very effective method for increasing barrier performance of OLED device. Gases and water in the organic evaporating system is having a strong influence as impurities to OLED device. CRYO pump is one of the very useful vacuum components to reduce above impurities. There for CRYO pump is faster than conventional TMP exhaust velocity of gases and water. So, we suggest new method to make a good vacuum condition which is CRYO Trap addition on OLED evaporator. Alignment accuracy is one of the key technologies to perform high resolution OLED device. In order to reduce vibration characteristic of CRYO pump, ULVAC has developed low vibration CRYO pumps to achieve high resolution alignment performance between Metal mask and substrate. This report also includes ULVAC's approach for these issues.