• 산업진흥연구
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• 제1권1호
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• pp.1-6
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• 2016

산화물반도체의 결정질특성과 비정질특성을 이해하기 이하여 AZO 박막과 IGZO 박막을 증착하고 열처리하여 물리적 화학적인 특성을 비교하였다. AZO 박막은 열처리온도가 올라갈수록 결정성이 높아졌으나 IGZO 박막은 열처리온도가 높을수록 비정질특성이 우수하였다. AZO 박막은 열처리에 따라서 PL, XPS 분석에서 화학적 이동이 나타났으나 IGZO 박막은 화학적 이동이 나타나지 않았다. AZO의 O 1s 결합 에너지는 531.5 eV였으며, IGZO 박막은 530 eV으로 낮았다.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.57-61
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• 1997

The effects of pH of solution on structural, electrical, and optical properties of CdS thin films prepared by solution growth method were investigated. With increasing pH of the solution, both crystallinity and transmittance of CdS thin film were deteriorated due to impurities and CdS particles, which were produced by homogeneous nucleation and adsorbed on the surface of CdS thin films. The films were strongly adherent to substrates and has low resistivity of 10~$10^2{\omega}cm$ regrardless of deposition conditions. After annealing at 30$0^{\circ}C$ in Ar atmosphere, the resistivity decreased due to desorption of impurity ions as well as the formation of S vacancies, but after annealing above 35$0^{\circ}C$ it increased by an agglomeration of S vacancies. After annealing in air atmosphere, the film resistivity increased because of the formation of oxide particle in grain boundaries.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• Journal of Semiconductor Engineering
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• 제1권1호
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.88-91
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• 2024

The europium doped yttrium oxide (Y₂O₃:Eu³⁺) thin film was formed on a Si substrate by the conventional spin-coating process followed by rapid thermal annealing (RTA) treatment. The spinning profiles such as rotation speed, acceleration and holding times were controlled during the spin-coating process for the best condition of the Y₂O₃:Eu³⁺ thin film. The RTA treatment was conducted for several temperature in order to crystallize the spin coated film. The Y₂O₃:Eu³⁺ thin film presented best performance in the conditions of 4000 rpm, 30 s and 10 s of rotation speed, acceleration time and holding time, respectively, at a fixed RTA temperature of 900 ℃.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.242-242
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• 2012

Transparent oxide semiconductors are increasingly becoming one of good candidates for high efficient channel materials of thin film transistors (TFTs) in large-area display industries. Compare to the conventional hydrogenated amorphous silicon channel layers, solution processed ZnO-TFTs can be simply fabricated at low temperature by just using a spin coating method without vacuum deposition, thus providing low manufacturing cost. Furthermore, solution based oxide TFT exhibits excellent transparency and enables to apply flexible devices. For this reason, this process has been attracting much attention as one fabrication method for oxide channel layer in thin-film transistors (TFTs). But, poor electrical characteristic of these solution based oxide materials still remains one of issuable problems due to oxygen vacancy formed by breaking weak chemical bonds during fabrication. These electrical properties are expected due to the generation of a large number of conducting carriers, resulting in huge electron scattering effect. Therefore, we study a novel technique to effectively improve the electron mobility by applying environmental annealing treatments with various gases to the solution based Li-doped ZnO TFTs. This technique was systematically designed to vary a different lithium ratio in order to confirm the electrical tendency of Li-doped ZnO TFTs. The observations of Scanning Electron Microscopy, Atomic Force Microscopy, and X-ray Photoelectron Spectroscopy were performed to investigate structural properties and elemental composition of our samples. In addition, I-V characteristics were carried out by using Keithley 4,200-Semiconductor Characterization System (4,200-SCS) with 4-probe system.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.245-245
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• 2009

l-D nanostructured materials have much more attention because of their outstanding properties and wide applicability in device fabrication. Copper oxide(CuO) has been realized as a p-type metal oxide semiconductor with narrow band gap of 1.2 -1.5eV. Copper oxide nanostructures can be synthesized by various growth method such as oxidation reaction, thermal evaporation thermal decomposition, sol-gel. and Mostly CuO nanowire prepared on the Cu substrate such as Copper foil, grid, plate. In this study, CuO NWs were grown by thermal oxidation (at various temperatures in air (1 atm)) of Cu metal deposited on CuO (20nm)/$SiO_2$(250nm)/Si. A 20nm-thick CuO layer was used as an adhesion layer between Cu metal and $SiO_2$

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.387.1-387.1
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• 2016

Transparent materials are necessary for most photoelectric devices, which allow the light generation from electric energy or vice versa. Metal oxides are usual materials for transparent conductors to have high optical transmittance with good electrical properties. Functional designs may apply in various applications, including solar cells, photodetectors, and transparent heaters. Nanoscale structures are effective to drive the incident light into light-absorbing semiconductor layer to improve solar cell performances. Recently, the new metal oxide materials have inaugurated functional device applications. Nickel oxide (NiO) is the strong p-type metal oxide and has been applied for all transparent metal oxide photodetector by combining with n-type ZnO. The abrupt p-NiO/n-ZnO heterojunction device has a high transmittance of 90% for visible light but absorbs almost entire UV wavelength light to show the record fastest photoresponse time of 24 ms. For other applications, NiO has been applied for solar cells and transparent heaters to induce the enhanced performances due to its optical and electrical benefits. We discuss the high possibility of metal oxides for current and future transparent electronic applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권2호
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.284-284
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• 2011

Recently, the increasing degree of device integration in the fabrication of Si semiconductor devices, etching processes of nano-scale materials and high aspect-ratio (HAR) structures become more important. Due to this reason, etch selectivity control during etching of HAR contact holes and trenches is very important. In this study, The etch selectivity and etch rate of TEOS oxide layer using ACL (amorphous carbon layer) mask are investigated various process parameters in CH2F2/C4F8/O2/Ar plasma during etching TEOS oxide layer using ArF/BARC/SiOx/ACL multilevel resist (MLR) structures. The deformation and etch characteristics of TEOS oxide layer using ACL hard mask was investigated in a dual-frequency superimposed capacitively coupled plasma (DFS-CCP) etcher by different fHF/ fLF combinations by varying the CH2F2/ C4F8 gas flow ratio plasmas. The etch characteristics were measured by on scanning electron microscopy (SEM) And X-ray photoelectron spectroscopy (XPS) analyses and Fourier transform infrared spectroscopy (FT-IR). A process window for very high selective etching of TEOS oxide using ACL mask could be determined by controlling the process parameters and in turn degree of polymerization. Mechanisms for high etch selectivity will discussed in detail.