• 한국재료학회지
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• 제2권1호
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• pp.76-82
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• 1992

$TEOS-O_3$ 산화막은 깔개층 물질에 따라 증착속도가 변하는 특성을 나타낸다. 본 논문에서는 $TEOS-O_3$ 산화막의 깔개층 물질 의존성 이외에도 배선 밀도, 배선 간격에 따라 증착속도가 달라지는 패턴 의존성에 대하여 조사하였다. 또한 $TEOS-O_3$ 산화막의 깔개층 물질 의존성 및 패턴 의존성을 줄이기 위해 다층 배선에서 1차 배선후에 깔개층, 즉 TEOS-base 프라즈마 산화막 및 $SiH_4-base$ 프라즈마 산화막을 증착했을 때 $TEOS-O_3$ 산화막의 증착 특성을 조사하였다. 그리고 그 깔개층 물질에 $N_2$ 프라즈마 처리를 했을 때 $TEOS-O_3$ 산화막의 증착 특성에 대해 조사하였다. 그 결과 $TEOS-O_3$ 산화막에서 기판 위에 배선 밀도와 배선 간격에 따른 의존성은 깔개층물질이 $SiH_4-base$ 일때보다 TEOS-base 프라즈마 산화막인 경우 $N_2$ 프라즈마 처리를 하면 깔개층 물질 표면이 O-Si-N화 되므로써 의존성이 사라지게 된다.

• Transactions on Electrical and Electronic Materials
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• 제11권1호
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.6-11
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• 2019

For a wider application of laser direct patterning, selective laser ablation of indium tin oxide (ITO) film on transparent oxide semiconductor (TOS) thin film was carried out using a diode-pumped Q-switched Nd:YVO₄ laser at a wavelength of 1064 nm. In case of the laser ablation of ITO on indium gallium zinc oxide (IGZO) film, both of ITO and IGZO films were fully etched for all the conditions of the laser beams even though IGZO monolayer was not ablated at the same laser beam condition. On the contrary, in case of the laser ablation of ITO on zinc oxide (ZnO) film, it was possible to etch ITO selectively with a slight damage on ZnO layer. The selective laser ablation is expected to be due to the different coefficient of thermal expansion (CTE) between ITO and ZnO.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.354-355
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• 2009

In the fabrication of inverted top-emitting organic light emitting diodes (ITOLEDs), the sputtering process is needed for deposition of transparent conducting oxide (TCO) as top anode. Energetic particle bombardment, however, changes the physical properties of underlying layers. In this study, we examined plasma process effects on tungsten oxide ($WO_3$) hole injection layer (HIL). From our results, we suggest the theoretical mechanism to explain the correlation between the physical property changes caused by plasma process on $WO_3$ HIL and degradation of device performances.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.449-457
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• 2012

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• 한국전기전자재료학회논문지
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• 제34권4호
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• pp.242-245
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• 2021

In this work, we fabricated oxide on an n-type silicon substrate through local anodic oxidation (LAO) using atomic force microscopy (AFM). The resulting oxide thickness was measured and its correlation with load force, scan speed and applied voltage was analyzed. The surface oxide layer was stripped using a buffered oxide etch. Ohmic contacts were created by applying silver paste on the silicon substrate back face. LAO was performed at approximately 70% humidity. The oxide thickness increased with increasing the load force, the voltage, and reducing the scan speed. We confirmed that LAO/AFM can be used to create both lateral and, to some extent, vertical shapes and patterns, as previously shown in the literature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.203-212
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• 2010

In this paper, we present an analytical model for the first eigen energy level ($E_0$) of the carriers in the inversion layer in present generation MOSFETs, having ultrathin gate oxides and high substrate doping concentrations. Commonly used approaches to evaluate $E_0$ make either or both of the following two assumptions: one is that the barrier height at the oxide-semiconductor interface is infinite (with the consequence that the wave function at this interface is forced to zero), while the other is the triangular potential well approximation within the semiconductor (resulting in a constant electric field throughout the semiconductor, equal to the surface electric field). Obviously, both these assumptions are wrong, however, in order to correctly account for these two effects, one needs to solve Schrodinger and Poisson equations simultaneously, with the approach turning numerical and computationally intensive. In this work, we have derived a closed-form analytical expression for $E_0$, with due considerations for both the assumptions mentioned above. In order to account for the finite barrier height at the oxide-semiconductor interface, we have used the asymptotic approximations of the Airy function integrals to find the wave functions at the oxide and the semiconductor. Then, by applying the boundary condition at the oxide-semiconductor interface, we developed the model for $E_0$. With regard to the second assumption, we proposed the inclusion of a fitting parameter in the wellknown effective electric field model. The results matched very well with those obtained from Li's model. Another unique contribution of this work is to explicitly account for the finite oxide-semiconductor barrier height, which none of the reported works considered.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.806-808
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• 2008

We studied ink-jet printing for selective deposition of soluble oxide semiconductor to fabricate transistor. Sol-gel derived ZTO solution was synthesized for ink-jet printable solution. Transistors were produced by printing oxide layer between ITO electrodes. We demonstrated that ink-jet printed ZTO transistors work well and surface treatment significantly influences device performance.