• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.356-357
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• 2006

Tin oxide thin films have been prepared on display glass from mixtures of dibutyl tin diacetate as a tin source, oxygen as an oxidant by Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The relationships between the properties of tin oxide thin films and various reaction parameters such as the deposition temperature, deposition time and the oxygen gas flow rate were studied. As the deposition temperature increased, the texture plane of $SnO_2$ changed from (200) plane to denser (211) and (110) planes. Lower deposition temperature and thinner thickness of deposited film led to decreasing grain size, surface roughness and electrical resistivity of the formed thin films at $325{\sim}425^{\circ}C$. The properties of fabricated $SnO_2$ films are highly changed with variations of substrate temperature and deposition time.

• 한국재료학회지
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• 제16권10호
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• pp.619-623
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• 2006

Selective vapor deposition of conductive poly(3,4-ethylenedioxythiophene) (PEDOT), thin films has been carried out on self assembled monolayers patterned oxide substrate. Since the 3,4-ethylenedioxythiophene(EDOT) monomer can be polymerized only in the presence of oxidant such as $FeCl_3$, the PEDOT thin film is selectively deposited on patterned $FeCl_3$, which only adsorbs on the partly removed SAMs region due to the inability of $FeCl_3$ to adsorb on SAMs. Therefore, the partly removed SAMs can act as an adsorption layer for the $FeCl_3$ and also as a glue layer for the deposition of PEDOT, resulting in the significantly increased adhesion of PEDOT to $SiO_2$ substrate. The use of UV lithography and Cr patterned quartz mask provided the formation of SAMs patterns on oxide substrates, which allowed for the selective deposition of conductive PEDOT thin films.$^{oo}The$ new process was successfully developed for the selective deposition of PEDOT thin films on SAMs patterned oxide substrate, providing a new way for the patterning of vapor phase deposition of PEDOT thin films with accurate alignment and addressing the inherent adhesion issues between PEDOT and dielectrics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.178-178
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• 2010

With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2008년도 제34회 동계학술대회 초록집
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• pp.279-279
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• 2008

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• 한국재료학회지
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• 제28권9호
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• pp.516-521
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• 2018

Copper oxide thin films are deposited using an ultrasonic-assisted spray pyrolysis deposition (SPD) system. To investigate the effect of substrate temperature and incorporation of a chelating agent on the growth of copper oxide thin films, the structural and optical properites of the copper oxide thin films are analyzed by X-ray diffraction (XRD), field-emssion scanning electron microscopy (FE-SEM), and UV-Vis spectrophotometry. At a temperature of less than $350^{\circ}C$, three-dimensional structures consisting of cube-shaped $Cu_2O$ are formed, while spherical small particles of the CuO phase are formed at a temperature higher than $400^{\circ}C$ due to a Volmer-Weber growth mode on the silicon substrate. As a chelating agent was added to the source solutions, two-dimensional $Cu_2O$ thin films are preferentially deposited at a temperature less than $300^{\circ}C$, and the CuO thin film is formed even at a temperature less than $350^{\circ}C$. Therefore the structure and crystalline phase of the copper oxide is shown to be controllable.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.582-582
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• 2013

Oxide TFT (thin film transistor) active channel layer에 대한 저온 열처리 공정은 투명하고 flexibility을 기반으로하는 display 산업과 AMOLED (active matrix organic light emitting diode) 분야 등 다양한 분야에서 필요로 하는 기술로서 많은 연구가 이루어지고 있다. 과거 active layer는 ALD (atomic layer deposition), CVD (chemical vapor deposition), pulse laser deposition, radio frequency-dc (RF-dc) magnetron sputtering 등과 같은 고가의 진공 장비를 이용하여 증착 되어져 왔으나 현재에는 진공 장비 없이 spin-coating 후 열처리 하는 저가의 공정이 주로 연구되어 지고 있다. Flexible 기판들은 일반적인 OTFT (oxide thin films Transistor)에 적용되는 열처리 온도로 공정 진행시 열에 의한 기판의 손상이 발생한다. Flexible substrate의 열에 의한 기판 손상을 막기 위해 저온 열처리 공정이 연구되고 있지만 기존 열처리와 비교하여 소자의 특성 저하가 동반 되었다. 본 연구에서는 Si 기판위에 SiO2 (100)를 절연층으로 증착하고 그 위에 IZO (indium zinc oxide) solution을 spin-coating 한뒤 $250^{\circ}C$ 이하의 온도에서 열처리하였다. 저온 공정으로 인하여 소자의 특성 저하가 동반 되었으므로 소자의 저하된 특성 복원하고자 post-treatment로 고가의 진공장비가 필요 없고 roll-to roll system 적용이 수월한 remote-type의 APP (atmospheric pressure plasma) 처리를 하였다. Post-treatment로 APP를 이용하여 $250^{\circ}C$ 이하에서 소자에 적용 가능한 on/off ratio를 얻을 수 있었다.

• 한국전기전자재료학회논문지
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• 제21권2호
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• pp.156-161
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• 2008

The fabrication of vanadium oxide films directly on Si(100) substrates by plasma atomic layer deposition(ALD) with vanadium oxytriisopropoxide(VOIP) and oxygen as the reactants have been performed at temperature ranging from 250 to $450^{\circ}C$. Growth rate of vanadium oxide was $2.8{\AA}$/cycle at $300{\sim}400^{\circ}C$ defined as ALD acceptable temperature window, Vanadium oxide has been shown the different phases at $250^{\circ}C$ and more than $300^{\circ}C$. It has been confirmed that the phase of the films deposited at $250^{\circ}C\;was\;V_2O_5$ type and that of the films above $300^{\circ}C\;was\;VO_2(T)$ type measured at room temperature, respectively. A large change in resistance and small temperature hysteresis corresponding to a temperature has been observed in the vanadium oxide film deposited at temperature $350^{\circ}C$.

• 한국세라믹학회지
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• 제33권4호
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• pp.441-447
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• 1996

Sb doped SnO2(ATO:Antinomy doped Tin Oxide) thin films were prepared by a DC magnetron spttuering method using oxide target and the deposition characteristics were investigated. The experimental conditions are as follows :Ar flow rate : 100 sccm oxygen flow rates ; 0-100 sccm deposition temperature ; 250 -40$0^{\circ}C$ DC sputter powder ; 150~550 W and sputtering pressure ; ; 2~7 mTorr. Deposition rate greatly depends not on the deposition temperature but on the reaction pressure oxygen flow rate and sputter power,. when the sputter powder is low ATO thin films with (110) preferred orientation are deposited. And when the sputter power is high (110) prefered orientation appeares with decreasing of oxygen flow rate and increasing of suputte-ring pressure.

• Transactions on Electrical and Electronic Materials
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• 제3권3호
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.