• 제목/요약/키워드: Oxide CMP

검색결과 154건 처리시간 0.033초

Quaternary Ammonium Polysulfone막의 제조 및 투과 특성 (I) - Quaternary Ammonium Polysulfone의 제조 - (The Preparation of Quaternary Ammonium Polysulfone and its Permeation Behavior (I) -Preparation of Quaternary Ammonium Polysulfone-)

  • 현진호;전종영;김종호;탁태문
    • 멤브레인
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    • 제6권2호
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    • pp.72-78
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    • 1996
  • 양이온성의 quaternary ammonium polysulfone인 AMPS는 2단계 과정을 통하여 제조하였다. 먼저, 폴리술폰을 chloromethyl methyl ether와 촉매로 ZnO를 사용하여 chloromethylation반응으로 CMPS를 제조하는 단계와 준비된 CMPS에 triethylamine을 반응시켜 quaternary ammonium기를 도입시키는 amination 단계로 이루어 진다.

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Chemical Mechnical Polishing(CMP) 공정후의 금속오염의 제거를 위한 건식세정 (Dry cleaning for metallic contaminants removal after the chemical mechanical polishing (CMP) process)

  • 전부용;이종무
    • 한국진공학회지
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    • 제9권2호
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    • pp.102-109
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    • 2000
  • chemical mechanical Polishing (CMP)공정 중 제거된 막과 연마재의 지꺼기를 제거하기 위하여 일반적으로 사용하는 scrubbing과 같은 기계적인 세정법으로는 기가급 소자 제조시에 요구되는 $10^{10}/\textrm{cm}^2$ 이하의 오염도에 도달하기 어렵다. 따라서 이러한 기계적인 세정법에 이어 충분히 제거되지 못한 금속오염물을 제거하기 위한 2차 세정이 요구된다. 본 논문에서는 리모트 플라스마 세정법과 UV/$O_3$ 세정법을 사용하여 oxide CMP 후에 웨이퍼 표면에 많이 존재하는 K, Fe, Cu등의 금속오염물을 제거하는데 대한 연구결과를 보고하고자 한다. 리모트 수소 플라스마 세정결과에 의하면, 세정시간이 짧을 수록, rf-power가 증가할수록 세정 효과가 우수한 것으로 나타났으며, CMP 공정 후 웨이퍼 표면에 특히 많이 존재하는 금속 불순물인 K, Fe, Cu 등의 오염 제거를 위한 최적 공정 조건은 세정시간이 1분, rf-power가 100 W인 것으로 나타났다. AFM 분석 결과에 의하면 rf-power의 증가에 따라 표면 거칠기가 미소하게 증가하는데 , 이것은 플라스마에 의한 손상 때문인 것으로 보이나 그 정도는 무시할만하다. 한편, UV/$O_3$ 세정의 경우에는 세정공정시간이 30 sec일때 가장 우수한 세정효과가 얻어졌다. 리모트 수소 플라스마 및 UV/$O_3$ 세정방법에 의한 Si 웨이퍼 표면의 금속 불순물 제거기구는 Si표면 금속오염의 하단층에 생성된 $SiO_2H^+$/ 및 $e^-$와 반응하여 $SiO^*$상태로 휘발될 때 금속불순물이 $SiO^*$에 묻어서 함께 제거되는 것으로 사료된다.

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DSS에서 $CeO_2$ 연마제의 첨가량과 분산시간이 TEOS 막에 미치는 특성연구 (A Study on the effect of TEOS film by Dispel8ion Time and Content of $CeO_2$ Abrasive)

  • 서용진;한상준;박성우;이영균;이성일
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.487-487
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    • 2009
  • One of the critical consumables in chemical mechanical polishing (CMP) is a specialized solution or slurry, which typically contains both abrasives and chemicals acting together to planarize films. In single abrasive slurry (SAS), the solid phase consists of only one type of abrasive particle. On the other hand, mixed abrasive slurry (MAS) consists of a mixture of at least two types of abrasive particles. In this paper, we have studied the CMP characteristics of mixed abrasive slurry (MAS) retreated by adding of $CeO_2$ abrasives within 1:10 diluted silica slurry (DSS). The slurry designed for optimal performance should produce reasonable removal rates, acceptable polishing selectivity with respect to the underlying layer, low surface defects after polishing, and good slurry stability. The modified abrasives in MAS are evaluated with respect to their particle size distribution, surface morphology, and CMP performances such as removal rate and non-uniformity. As an experimental result, we obtained the comparable slurry characteristics compared with original silica slurry in the viewpoint of high removal rate and low non-uniformity.

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산화막CMP의 연마균일도 향상을 위한 웨이퍼의 에지형상제어 (Wafer Edge Profile Control for Improvement of Removal Uniformity in Oxide CMP)

  • 최성하;정호빈;박영봉;이호준;김형재;정해도
    • 한국정밀공학회지
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    • 제29권3호
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    • pp.289-294
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    • 2012
  • There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

PMD-1 층의 물질변화에 따른 소자의 전기적 특성 (Electrical Characteristics of Devices with Material Variations of PMD-1 Layers)

  • 서용진;김상용;유석빈;김태형;김창일;장의구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 D
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    • pp.1327-1329
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    • 1998
  • It is very important to select superior inter-layer PMD(Pre Metal Dielectric) materials which can act as penetration barrier to various impurities created by CMP processes. In this paper, hot carrier degradation and device characteristics were studied with material variation of PMD-1 layers, which were split by LP-TEOS, SR-Oxide, PE-Oxynitride, PE-Nitride, PE-TEOS films. It was observed that the oxynitride and nitride using plasma was greatly decreased in hot carrier effect in comparison with silicon oxide. Consequently, silicon oxide turned out to be a better PMD-1 material than PE-oxynitride and PE-nitride. Also, LP-TEOS film was the best PMD-1 material Among the silicon oxides.

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수열처리에 의한 세리아가 코팅된 실리카 연마재의 제조 및 Oxide Film의 연마특성 (Preparation of Ceria Coated Silica Abrasive by Hydrothermal Treatment and Polishing Rate on Oxide Film)

  • 유대선;김대성;이승호
    • 한국재료학회지
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    • 제15권12호
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    • pp.818-823
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    • 2005
  • Sub-micron colloidal silica particles coated with nano-sized ceria were prepared by mixing of its silica and cerium salts hydrolysis, and modified by hydrothermal reaction. By using the slurries with and without hydrothermal modification containing above particles, oxide film coated on silicon wafer was polished. The modified slurries had higher polish rate due to increase of ceria fraction to silica through hydrothermal reaction. They revealed higher stability in wide range of pH $2\~10$ than ceria coated silica slurries without its modification.

고온 패드 컨디셔닝 후 열산화막 연마 메커니즘 연구 (Study on Polishing Mechanism of Thermal Oxide Film after High-Temperature Conditioning)

  • 최권우;김남훈;서용진;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.193-194
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    • 2005
  • By the high-temperature pad conditioning process: The slurry residues in pores and grooves of the polishing pad were clearly removed. These clear pores and enlarged grooves made the slurry attack the oxide surface. The changed slurry properties by high-temperature pad conditioning process made the oxide surface hydro-carbonate to be removed easily.

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Effect of Particle Size of Ceria Coated Silica and Polishing Pressure on Chemical Mechanical Polishing of Oxide Film

  • Kim, Hwan-Chul;Lim, Hyung-Mi;Kim, Dae-Sung;Lee, Seung-Ho
    • Transactions on Electrical and Electronic Materials
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    • 제7권4호
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    • pp.167-172
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    • 2006
  • Submicron colloidal silica coated with ceria were prepared by mixing of silica and nano ceria particles and modified by hydrothermal reaction. The polishing efficiency of the ceria coated silica slurry was tested over oxide film on silicon wafer. By changing the polishing pressure in the range of $140{\sim}420g/cm^2$ with the ceria coated silica slurries in $100{\sim}300nm$, rates, WIWNU and friction force were measured. The removal rate was in the order of 200, 100, and 300 nm size silica coated with ceria. It was known that the smaller particle size gives the higher removal rate with higher contact area in Cu slurry. In the case of oxide film, the indentation volume as well as contact area gives effect on the removal rate depending on the size of abrasives. The indentation volume increase with the size of abrasive particles, which results to higher removal rate. The highest removal rate in 200 nm silica core coated with ceria is discussed as proper combination of indentation and contact area effect.

STI 채널 모서리에서 발생하는 MOSFET의 험프 특성 (The MOSFET Hump Characteristics Occurring at STI Channel Edge)

  • 김현호;이천희
    • 한국시뮬레이션학회논문지
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    • 제11권1호
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    • pp.23-30
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    • 2002
  • An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1] In this paper we fabricated N, P-MOSFEET tall analyse hump characteristics in various rounding oxdation thickness(ex : Skip, 500, 800, 1000$\AA$). As a result we found that hump occurred at STI channel edge region by field oxide recess. and boron segregation(early turn on due to boron segregatiorn at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess( 20nm), wet oxidation etch time(19HF,30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and fate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

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