• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.353-359
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• 2012

A highly efficient charge pump that minimizes the reverse charge sharing current (in short, reverse current) is proposed. The charge pump employs auxiliary capacitors and diode-connected MOSFET along with an early clock to drive the charge transfer switches; this new method provides better isolation between stages. As a result, the amount of reverse current is reduced greatly and the clock driver can be designed with reduced transition slope. As a proof of the concept, a 1.1V-to-9.8 V charge pump was designed in a $0.35{\mu}m$ 18 V CMOS technology. The proposed architecture shows 1.6 V ~ 3.5 V higher output voltage compared with the previously reported architecture.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.33-34
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• 2017

This paper presents a linear droop control scheme based on the generation costs of DGs in an autonomous DC microgrid. Unlike the proportional power sharing of the conventional droop control, in the proposed control algorithm, the minimum output voltage range is adjusted and the droop coefficients are regulated according to the generation costs of DGs. As a result, the DGs with lower costs supplies more power in comparison with those with higher costs. Therefore, total generation cost of the system is reduced significantly. The proposed method is simple to implement and it does not require the centralized controller and communication links.

• Transactions on Electrical and Electronic Materials
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• v.16 no.5
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• pp.241-249
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• 2015

Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• Journal of Power Electronics
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• v.15 no.2
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• pp.455-468
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• 2015

A microgrid (MG) with integrated renewable energy resources can benefit both utility companies and customers. As a result, they are attracting a great deal of attention. The control of a MG is very important for the stable operation of a MG. The droop-control method is popular since it avoids circulating currents among the converters without using any critical communication between them. Traditional droop control methods have the drawback of an inherent trade-off between power sharing and voltage and frequency regulation. An adaptive droop control method is proposed, which can operate in both the island mode and the grid-connected mode. It can also ensure smooth switching between these two modes. Furthermore, the voltage and frequency of a MG can be restored by using the proposed droop controller. Meanwhile, the active power can be dispatched appropriately in both operating modes based on the capacity or running cost of the Distributed Generators (DGs). The global information (such as the average voltage and output active power of the MG and so on) required by the proposed droop control method to restore the voltage and frequency deviations can be acquired distributedly based on the Multi Agent System (MAS). Simulation studies in PSCAD demonstrate the effectiveness of the proposed control method.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.143-151
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• 2018

In this paper, a novel hybrid configuration combining a phase-shift full-bridge (PSFB) and a half-bridge resonant LLC converter is proposed for the On-Board Charger of Electric Vehicles (EVs). In the proposed converter, the PSFB converter shares the lagging-leg switches with half-bridge resonant converter to achieve the wide ZVS range for the switches and to improve the efficiency. The output voltage is modulated by the effective-duty-cycle of the PSFB converter. The proposed converter employs an active reset circuit composed of an active switch and a diode for the transformer which makes it possible to achieve zero circulating current and the soft switching characteristic of the primary switches and rectifier diodes regardless of the load, thereby making the converter highly efficient and eliminating the reverse recovery problem of the diodes. In addition an optimal power sharing strategy is proposed to meet the specification of the charger and to optimize the efficiency of the converter. The operation principle the proposed converter and design considerations for high efficiency are presented. A 6.6 kW prototype converter is fabricated and tested to evaluate its performance at different conditions. The peak efficiency achieved with the proposed converter is 97.7%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).