• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.555-558
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• 2002

The general ways of the anti-islanding can be classified into the active method and passive method. The passive method which use only the voltage information when power failure occurs has much possibility of the wrong detection. And the active method detects the change of the voltage frequency as instantaneously changing the frequency of the inverter output current. Therefore, in this paper, the method to inject arbitrary order harmonics into controlled current is proposed. In this method islanding can be detected by measuring the amount of load voltage of injected harmonics order. And as a current control method predictive control method is used, which make actual current accurately to track reference current by Instantaneously computing converter output voltage and has fast response in transient state. This parer proposed method was verified by simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2152-2154
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• 1999

In this paper, we suggested the design rule of high-voltage rectangular waveform generator working in low frequency domain (5Hz $\sim$ 60Hz). Most of the commonly used power electronic switching devices have voltage ratings up to several kV. So it is difficult to design and fabricate high-voltage switching systems with the power electronic devices alone. We have combined IGBTC(1200V, 50A) with the specially designed transformer to get the high-voltage rectangular waveforms up to 40kV. In this work. next two things are the main factors. The first one is design of transformer working low-frequency domain close to 5Hz. And the second one is additional voltage source to floating the transformer voltage output. As a result, we can get frequency-variable and high-voltage rectangular voltage waveform and this can be a more efficient power source of sandpaper manufacturing process.

• Journal of information and communication convergence engineering
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• 제6권3호
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.307-310
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• 2002

A design for the input filter and the output filter of a single-phase UPS system is proposed. And also, this paper describes a reduction of the DC voltage ripple of a single-phase UPS. The input power of proposed UPS fluctuates with twice frequency of the utility source, which causes DC voltage fluctuation. The reduction of the DC voltage fluctuation requires a large DC link capacitor. The proposed method uses a LC series resonant filter paralleled with a conventional smoothing capacitor. The effectiveness of the proposed method was confirmed by simulation results.

• 전력전자학회논문지
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• 제20권4호
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• pp.356-362
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• 2015

This paper presents a current control strategy in the synchronous reference frame for a single-phase PWM converter, which ensures sinusoidal input current control under the distorted source voltage and frequency condition. Given that the distorted source voltage distorts the phase angle for PWM converter control, the input current contains the same harmonics as the source voltage. Aside from the distorted voltage, the variation in source frequency reduces the performance of input current control. To achieve sinusoidal input current control under the distorted source voltage and frequency condition, this paper proposes a compensation strategy of current reference with the distortion component extracted from the phase angle and a detection strategy of frequency variation from the output of a synchronous reference frame phase-lock loop. The experimental results confirm the validity of the proposed method under the distorted source voltage and frequency condition.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.403-405
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• 2007

This paper presents the over-modulation strategy and indirect vector control drive of NPC type PWM inverter. NPC inverter has three level phase voltage output.It can perform in high voltage through assembling switching components. It has less harmonics and surge voltage stress at motor terminals than the 2 level inverter in same switching frequency through 3 level voltage. The conventional railway vehicle has used the vector control to MI=0.907 and the slip-frequency control from MI=0.907 to six-step mode. The slip-frequency control has bad motive power and slow torque control response. But vector control has good motive power and can instant torque control. In this paper, output voltage is controlled linearly from linear region to six-step mode by using over-modulation strategy. And NPC inverter is used.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• 전기학회논문지
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• 제57권7호
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• pp.1187-1194
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• 2008

This paper presents a high-power electronic ballast for a metal-hallide lamp(MHL) that employs frequency modulation(FM) technique to eliminate acoustic resonance(AR). The proposed ballast consists of a full-bridge rectifier, a power factor correction(PFC) circuit, a full-bridge(FB) inverter, an ignitor using LC resonance and an FM control circuit. Whereas a manual PFC provides advantages in terms of high reliability and low cost for constructing the circuit, it is difficult to supply a stable voltage because of the output voltage ripple that occurs with a period of 120Hz. Although the ballast can be designed with a small size and a light weight if it is driven at a switching frequency between 1 and 100 kHz, AR will occur if the eigen-value frequency of the lamp coincides with the inverter's operation frequency. The operation frequency was modulated in real time according to the output voltage ripple to compensate for the variation in power supplied to the lamp and eliminate AR. Performance of the proposed technique was validated through numerical analysis, computer simulation using PSPICE and by applying it to an electronic ballast for a prototype 1kW MHL.

• Journal of electromagnetic engineering and science
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• 제18권1호
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• pp.20-28
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• 2018

The time synchronization of each sub-unit of a pulsed generator is important to generate an output high-power radio frequency (RF) signal. To obtain the time synchronization between an input RF signal fed by an external source and an electron beam produced by an electric pulse generator, the influence of different charging voltages on a delay and a rise time of the output pulse waveform in the electric pulse generator should be carefully considered. This paper aims to study the timing characteristics of the delay and the rise time as a function of different charging voltages with a peak value of less than -35 kV in the high-voltage pulse generator, including a trigger generator (TG) and a pulse-forming line (PFL). The simulation has been carried out to estimate characteristics in the time domain, in addition to their output high-voltage amplitude. Experimental results compared with those obtained by simulation indicate that the delay of the output pulses of the TG and PFL, which are made by controlling the external triggering signal with respect to different charging voltages, is getting longer as the charging voltage is increasing, and their rise times are inversely proportional to the amplitude of the charging voltage.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권3호
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• pp.133-139
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• 2003

In this paper, a new control scheme of Class-E inverter for Induction Heating (IH) Jar applications with clamped voltage characteristics using Pulse-Frequency-Modulation (PFM) is introduced. To reduce the voltage stress of switch, the proposed PFM control scheme doesn't need any auxiliary circuit in comparison to a family of Active Clamped Class-E (ACCE) inverter. It can decrease voltage stress of switch through modulation of switching frequency. The Class-E inverter using the proposed control scheme has the advantage of not only the same output power when it is compared with a Hybrid-Active Clamped Class-E (Hybrid-ACCE) inverter but also Zero-Voltage-Switching (ZVS), which are characteristics of conventional Class-E and ACCE inverter. The control principles and analysis of proposed method are explained in detail and its validity is verified through simulation and experimental results.