• Journal of Electrical Engineering and Technology
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• v.6 no.6
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• pp.842-848
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• 2011

The current study proposes the design of a hybrid series-parallel resonant converter (SPRC) and a three-stage Cockcroft-Walton voltage multiplier for precisely adjusting the power generated by a continuous wave (CW) $CO_2$ laser. The design of a hybrid SPRC, called LCC resonant converter, is described, and the fundamental approximation of a high-voltage and high-frequency (HVHF) transformer with a resonant tank is discussed. The results of the current study show that the voltage drop and ripple of a three-stage Cockcroft-Walton voltage multiplier depend on frequency. The power generated by a CW $CO_2$ laser can be precisely adjusted by a variable-frequency controller using a DSP (TMS320F2812) microprocessor. The proposed LCC converter could be used to obtain a maximum laser output power of 23 W. Moreover, it could precisely adjust the laser output power within 4.3 to 23 W at an operating frequency range of 187.5 to 370 kHz. The maximum efficiency of the $CO_2$ laser system is approximately 16.5%, and the minimum ripple of output voltage is about 1.62%.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.4_1
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• pp.377-385
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• 2021

High voltage direct current(HVDC) systems has been an alternative method of a power transmission to replace high voltage alternate current(HVAC), which is a traditional AC transmission method. Due to technical limitations, Line commutate converter HVDC(LCC-HVDC) was mainly used. However, result from many structural problems of LCC-HVDC, the voltage source converter HVDC(VSC-HVDC) are studied and applied recently. In this paper, after analyzing the reactive power and output voltage ripple, which are the main problems of LCC-HVDC, the characteristics of each HVDC are summarized. Based on this result, a new LCC-HVDC structure is proposed by combining LCC-HVDC with the MMC structure, which is a representative VSC-HVDC topology. The proposed structure generates lower reactive power than the conventional method, and greatly reduces the 12th harmonic, a major component of output voltage ripple. In addition, it can be easily applied to the already installed LCC-HVDC. When the proposed method is applied, the control of the reactive power compensator becomes unnecessary, and there is an advantage that the cut-off frequency of the output DC filter can be designed smaller. The validity of the proposed LCC-HVDC is verified through simulation and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.2
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• pp.154-162
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• 2000

A technique to suppress the low frequency ripple voltage of the DC output ${\gamma}$oltage in three-phase buck d diode rectifiers is presented in this paper. The proposed pulse frequency modulation method is employed to r regulate the output voltage of the buck diode rectifiers and guarantee zero-current switching of the switch over the Vvide load range. The pulse frequency control method used in tIns paper shows generally good p performance such as low THD of the input line current and unity power factor. In addition, the pulse f freιluency method can be effectively used to suppress the low frequency voltage ripple appeared in the dc output voltage. The proposed technique illustrates its validity and effectiveness through the respective s simulations and experiments.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1593-1600
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• 2015

This paper proposes a novel compensation algorithm of current offset error for single-phase linear compressor in home appliances. In a half-bridge inverter, current offset error may cause unbalanced DC-link voltage when the DC-link is comprised of two serially connected capacitors. To compensate the current measurement error, the synchronous reference frame transformation is used for detecting the measurement error. When an offset error occurs in the output current of the half-bridge inverter, the d-axis current has a ripple with frequency equal to the fundamental frequency. With the use of a proportional-resonant controller, the ripple component can be removed, and offset error can be compensated. The proposed compensation method can easily be implemented without much computation and additional hardware circuit. The validity of the proposed algorithm is verified through experimental results.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.300-302
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• 1995

This paper describes a current control method for a single-phase PWM inverter. The proposed PWM inverter utilizes the instantaneous control method which is based on the real-time digital feedback control and the microprocessor-based deadbeat control. For the deadbeat current controller, the system's order becomes a high order and increases computation delay time. Therefore, The delay time produces current ripple. To minimize the current ripple, a new method based on deadbeat control theory for current regulation is proposed. It is constructed by a reduced-order state observer which predicts the output current in next sampling instant.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.1
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• pp.33-39
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• 2022

A multi-phase brushless direct current (BLDC) motor is widely used in large-capacity electric propulsion systems such as submarines and electric ships. In particular, in the field of military submarines, the polyphaser motor must suppress torque ripple in various failure situations to reduce noise and ensure stable operation for a long time. In this paper, we propose a polyphaser current control method that can improve efficiency and reduce torque ripple by minimizing the increase in stator winding loss at maximum output torque by controlling the phase angle and amplitude of the steady-state current during open circuit failure of the stator winding. The proposed control method controls the magnitude and phase angle of the healthy phase current, excluding the faulty phase, to compensate for the torque ripple that occurs in the case of a phase open failure of the motor. The magnitude and phase angle of the controlled steady-state current are calculated for each phase so that copper loss increase is minimized. The proposed control method was verified using hardware-in-the-loop simulation (HILS) of a 12-phase BLDC motor. HILS verification confirmed that the increase in the loss of the stator winding and the magnitude of the torque ripple decreased compared with the open phase fault of the motor.

• Journal of Power Electronics
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• v.16 no.3
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• pp.832-839
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• 2016

In this study, the performance of a direct current (DC)-DC buck converter is analyzed in the presence of non-idealities in passive components and semiconductor devices. The effect of these non-idealities on the various design issues of a DC-DC buck converter is studied. An improved expression for duty cycle is developed to compensate the losses that occur because of the non-idealities. The design equations for inductor and capacitor calculation are modified based on this improved expression. The effect of the variation in capacitor equivalent series resistance (ESR) on output voltage ripple (OVR) is analyzed in detail. It is observed that the value of required capacitance increases with ESR. However, beyond a maximum value of ESR (r_c,max), the capacitor is unable to maintain OVR within a specified limit. The expression of r_c,max is derived in terms of specified OVR and inductor current ripple. Finally, these theoretical studies are validated through MATLAB simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.109-116
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• 2016

This paper proposes an analytic model for four-switch inverter (FSI)-driven wye (Y) or delta (Δ)-connected motors with a current ripple reduction algorithm. FSIs employ four switches in controlling three-phase load instead of using six switches. They have split dc-link stage, and due to this inherent structure there exists the voltage difference between upper and lower capacitors, which results in distortion of the inverter output voltage. To study characteristics of FSIs, this paper presents an advanced simulation models of FSI-driven control system for 3-phase motor that can has a wire connection either Y or Δ. In addition, this paper introduces a current ripple reduction scheme that mitigates degradation of control performance due to the voltage difference between the dc-link capacitors. The validity of the proposed method and the analytic model is verified by simulations and experiments carried out with 1-HP induction machine with Y or Δ-connection

• Journal of the Korean Solar Energy Society
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• v.32 no.6
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• pp.106-112
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• 2012

As a fuel cell converts the chemical energy of the fuel cell into electrical energy by electrochemical reaction, the fuel cell system is uniquely integrated technique including fuel processor, fuel cell stack, power conditioning system. The residential fuel cell-PCS(Power Conditioning System) needs to convert efficiently the DC current produced by the fuel cell into AC current using single-phase DC-AC inverter. A single-phase DC-AC inverter has naturally low frequency ripple which is twice frequency of the output current. This low frequency(120Hz) ripple reduces the efficiency of the fuel cell. This paper presents notch filter with IP voltage controller to reject specific 120Hz current ripple in single-phase inverter. The notch filter is designed that suppress just only specific frequency component and no phase delay. Finally, the proposed notch filter design method has been verified with computer simulation and experimentation.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.