Effect of Non-Idealities on the Design and Performance of a DC-DC Buck Converter

Abstract

In this study, the performance of a direct current (DC)-DC buck converter is analyzed in the presence of non-idealities in passive components and semiconductor devices. The effect of these non-idealities on the various design issues of a DC-DC buck converter is studied. An improved expression for duty cycle is developed to compensate the losses that occur because of the non-idealities. The design equations for inductor and capacitor calculation are modified based on this improved expression. The effect of the variation in capacitor equivalent series resistance (ESR) on output voltage ripple (OVR) is analyzed in detail. It is observed that the value of required capacitance increases with ESR. However, beyond a maximum value of ESR (r_c,max), the capacitor is unable to maintain OVR within a specified limit. The expression of r_c,max is derived in terms of specified OVR and inductor current ripple. Finally, these theoretical studies are validated through MATLAB simulation and experimental results.

I. INTRODUCTION

Direct current (DC)–DC converters are widely used as power supply in various applications [1]-[4]. Several applications, such as aerospace, military, chemical refineries, and mines, require highly regulated, optimally designed, and compact power supplies. For such applications, an optimum design of inductance and capacitance for buck converter is reported in [5], [6]. In all practical DC–DC converters, power loss occurs because of the internal resistances of inductors, capacitors, and non-ideal switching devices. Most power electronic textbooks and papers have neglected some or all these non-ideal elements while analyzing and designing DC–DC converters [7]-[11]. However, this condition is unacceptable for an accurate and well-designed power supply because these non-idealities affect the desired values of the duty cycle, inductor, and capacitor of a DC–DC converter [12], [13]. For example, the expression for the duty cycle of an ideal buck converter is

where Vo is the output voltage, and Vg is the input voltage.

However, this relation does not remain valid for a non-ideal buck converter. Owing to the parasitic resistances of inductor, capacitor, diode, and switch, practical DC–DC converters have power losses. Therefore, the actual duty cycle of a non-ideal DC–DC buck converter should be greater than the ideal duty cycle given in Equ. (1) to compensate these losses. An improved expression for this actual duty cycle is derived in this study.

Similarly, the equivalent series resistance (ESR) of an output capacitor plays an important role in the design of capacitors [14]. As the ESR increases, the output voltage ripples (OVR) also increases, thereby reducing the effectiveness of filter capacitors. Moreover, high ESR may lead to instability and increase the power loss in converters [15]. Therefore, arbitrary selection of ESR is inadvisable for a precisely designed DC–DC buck converter. However, the ESR of a capacitor is a parasitic parameter that cannot be avoided by capacitor manufacturers. Nonetheless, power supply designers always prefer a capacitance with low ESR. No analytical solution is available in the literature to evaluate the upper limit of ESR that can be used without exceeding the specified OVR at a particular switching frequency. In this study, a formula for the maximum value of ESR is developed through an in-depth analysis of capacitor voltage ripples to select a capacitor with proper ESR.

The remainder of this paper is organized as follows to resolve the above-mentioned issues for a buck converter: First, a detailed analysis of a non-ideal buck converter is presented. Second, improved relationships for duty cycle, inductance, and capacitance design are proposed. Third, the analytical expression for maximum allowable ESR for specified OVR is proposed. Finally, MATLAB simulations and experimental results are obtained to confirm these theoretical studies.

 

II. ANALYSIS OF A NON-IDEAL DC–DC BUCK CONVERTER

The power circuit of a non-ideal DC–DC buck converter is shown in Fig. 1. All symbols have a standard meaning, as indicated in Table I. The buck converter is operating in a continuous current conduction mode with duty cycle D and switching frequency f (or switching period T) [7]. The voltage and current equations of the buck converter during the switch-on period (0 < t ≤ DT) and the switch-off period (DT < t ≤ T) are expressed below:

Fig. 1.Non-ideal DC–DC buck converter.

TABLE IBUCK CONVERTER SPECIFICATIONS

Mode 1: Switch-on (0 < t ≤ DT)

Mode 2: Switch-off (DT

A. Steady-State Analysis

For steady-state analysis, the time variables are substituted by their respective DC values as [8]

iL (t) = IL, vg (t) = Vg , vc (t) = Vc vo (t) = Vo.

According to the principle of inductor volt-second balance, in the steady-state, the average inductor voltage must be equal to zero.

Similarly, according to the principle of capacitor charge balance, in the steady-state, the average capacitor current must be equal to zero.

The average output voltage of the buck converter is

By substituting Equs. (2) and (5) into Equ. (8), we obtain

Substituting Equs. (3) and (6) into Equ. (9) obtains

Similarly, substituting Equs. (4), (7), and (9) into Equ. (10) gives

Replacing Equ. (12) into Equ. (11) provides the relationship for average output voltage as

where Dꞌ = 1 − D.

Equ. (14) depicts that the output voltage of the buck converter depends on non-idealities and load resistance.

The output voltage variation versus duty cycle plot is shown in Fig. 2 at a constant input voltage and different load resistances. For a particular duty cycle, the non-ideal buck converter produces an output voltage less than that of the ideal buck converter. The output voltage decreases further as the load resistance is decreased. Fig. 3 shows the output voltage variation for different values of input voltages at constant R. For a particular duty cycle, the difference between the output voltage of ideal and non-ideal buck converter becomes larger as input voltage increases. Therefore, the metal oxide semiconductor field-effect transistor (MOSFET) switch should be kept ON for an extended time to achieve the same output voltage in the presence of non-idealities. In other words, the actual duty cycle must be greater than the ideal duty cycle given by Equ. (1).

Fig. 2.Output voltage variation with duty cycle at various R and constant Vg.

Fig. 3.Output voltage variation with duty cycle at various Vg and constant R.

An improved expression of actual duty cycle is derived by solving Equ. (14) as

where Dideal = Vo/Vg is the duty cycle for an ideal buck converter.

The modified duty cycle D in Equ. (15) and the ideal duty cycle Dideal in Equ. (1) are plotted with the desired output voltage (Vo), as shown in Fig. 4. It verifies that the actual duty cycle should be greater than the ideal duty cycle to obtain the desired output voltage.

Fig. 4.Duty cycle variation with output voltage.

B. Inductor Current Ripple (ICR) and Inductor Design

Let xL be the ICR factor and ΔiL be the ripple current such that ΔiL= xLIL.

The magnitude of ripple current ΔiL in the steady-state is

Substituting IL from Equ. (12),

Replacing ΔiL= xLIL= xLVO/R and rearranging Equ. (17),

Equ. (18) provides the design value of inductance for the desired ICR in terms of converter parameters and non-ideal elements. The required inductance is calculated for ideal and non-ideal buck converters and is plotted with respect to duty cycle in Fig. 5, which depicts clearly that in the non-ideal case, the required inductance value is more than the ideal case. The difference becomes significant at low duty cycles.

Fig. 5.Inductance variation with duty cycle.

C. OVR and Capacitor Design

The capacitor current and voltage ripple waveforms in the steady-state are shown in Fig. 6. If the ESR of output capacitor is considered, then the OVR Δvo consists of the following two components:

Fig. 6.Capacitor current and voltage ripple waveforms.

1. Voltage ripple caused by capacitor (Δvc)

2. Voltage ripple caused by the presence of ESR (Δvrc)

Analysis during switch-on (0 < t ≤ DT): The capacitor current dynamics can be given as [16]

The voltage ripple contribution by the capacitor itself is

where Δvc(0) is the initial voltage across the capacitor at t = 0. The voltage ripple contribution by the ESR of the capacitor is

Therefore, the total voltage ripple during the switch-on period is

The minimum value of Δvo(t) occurs at time t1 and is given by

Analysis during switch-off (DT < t ≤ T): The capacitor current dynamics can be given as

The voltage ripple contribution by the capacitor itself is

where Δvc(DT) is the initial voltage across the capacitor at t = DT. In the steady-state, Δvc(DT) = Δvc(0).

The voltage ripple contribution by the ESR of the capacitor is

Therefore, the total voltage ripple during the switch-off period is

The maximum value of Δvo(t) occurs at time t2 and is given by

1) Voltage Ripples: The total peak-to-peak OVR is

Substituting the values from Equs. (23) and (29) into Equ. (31) and simplifying them gives

Letting rc = 0 gives the OVR for the ideal capacitor as available in the literature.

We can also find the contribution of capacitor voltage ripple and ESR voltage ripple in the peak-to-peak OVR.

The ripple voltage contribution by the capacitor is

Δvc = Δvc(t2)-Δvc(t1).

The ripple voltage contribution by ESR is

Δvrc = Δvrc(t2)-Δvrc(t1).

By substituting the values from Equs. (24) and (30), we have

The three voltage ripple variations defined in Equs. (32)-(34) are plotted with respect to ESR, as shown in Fig. 7. From this figure, with an increase in ESR, Δvrc increases at a faster rate than Δvc decreases, thereby causing a net increase in Δvo. However, as the value of rc increases beyond rc,max, Δvrc becomes higher than Δvo, which is practically impossible. This result implies that the capacitor is no longer able to keep OVR within the specified limit for rc > rc,max. The exact relation for this rc,max is derived later.

Fig. 7.Variation in voltage ripples with ESR.

2) Output Capacitor Design: Let the specified maximum OVR be Δvom. The capacitor is designed such that the following condition must be satisfied:

By substituting Δvo from Equ. (32) and simplifying it, gives

Equ. (36) is a quadratic constraint in C. It is solved to generate the minimum value of the capacitor C as

This equation provides the value of minimum capacitance required for rc≤rc,max.

3) Derivation for Maximum Permissible ESR: The additional term in Equ. (32) appears because of the presence of ESR. As ESR increases, OVR also increases. If the ESR of capacitor is not selected properly, then it may increase the total OVR beyond the maximum permissible value. Therefore, the relationship for the maximum permissible value of ESR for the specified OVR and switching frequency should be determined. In Equ. (37), Cmin must be a real quantity that satisfies the following condition:

On simplifying,

Therefore, the maximum permissible value of ESR (rc,max) for specified OVR (Δvom)and ICR( ΔiL) is given by

If the ESR value is greater than the rc,max in Equ. (40), then the capacitor will not be able to keep the steady-state OVR in the specified limit. This condition is verified by the experimental results in the subsequent section.

Substituting Equ. (40) into Equ. (37) obtains the minimum value of capacitor at rc = rc,max as

From Equ. (32), for an ideal capacitor (rc = 0), the minimum value of C is

Equ. (41) provides the minimum capacitance required for the worst-case ESR (rc,max). Fig. 8 shows the variation in minimum capacitance value as a function of ESR. The capacitor value increases with an increase in ESR. At rc = rc,max, the capacitor value becomes double that of with rc = 0. For rc > rc,max , the capacitance value is a complex value. However, as shown in Fig. 8, MATLAB simulation plots only the real part.

Fig. 8.Value of the minimum capacitance at different ESR.

Substituting the values of ΔiL from Equ. (17) into Equ. (40),

This relation depicts that for specified OVR, the maximum permissible value of ESR (rc,max) is proportional to switching frequency. Therefore, as the switching frequency of the converter increases, the power supply designer is allowed to use a high ESR capacitor without violating the OVR constraint. Fig. 9 shows the variation in rc,max with frequency. If the switching frequency is 50 kHz, then the designer may use a capacitor with an ESR of 0.6 Ω. As the frequency increases, the required capacitor value decreases.

Fig. 9.Maximum permissible ESR (rc,max) vs. frequency.

 

III. SIMULATION AND EXPERIMENTAL RESULTS

For MATLAB simulation, the buck converter parameters given in Table I are used. For given specifications, according to the relation proposed in Equ. (15), the actual duty cycle is calculated as 0.6415, which is greater than the ideal duty cycle (=0.6). For this actual duty cycle, the inductance value is calculated as 490 μH using Equ. (18). The maximum value of ESR(rc,max) and the minimum capacitance (Cmin) are calculated as 0.2398 Ω and 50 μF, respectively, using Equs. (40) and (41) for the OVR and ICR specified in Table I.

The simulated output voltage for ideal and actual duty cycles is shown in Fig. 10. The results confirm that for ideal duty cycle D = 0.6, the output voltage is 11.2 V; for actual duty cycle D = 0.6415, the output voltage is settled to 12 V (as desired).

Fig. 10.Simulated output voltage response for ideal and non-ideal duty cycles.

We consider four cases for four different values of ESR to investigate the effect of ESR variation on OVR. In each case, the total OVR Δvo, the ripple caused by capacitor Δvc and the ripple caused by ESR Δvrc are evaluated and plotted for two switching cycles, as discussed below.

Case 1 (rc = 0): This is the case for an ideal capacitor. However, such a capacitor cannot be obtained in practice. The voltage ripples are shown in Fig. 11(a). The voltage ripple Δvo is the same as Δvc. The peak-to-peak OVR is 0.06 V.

Fig. 11.Simulated voltage ripple waveforms for different ESR values (a) rc = 0, (b) rc = 0.1 Ω (rc < rc,max), (c) rc = 0.2398 Ω (rc = rc,max), and (d) rc = 0.4Ω (rc > rc,max).

Case 2 (rc = 0.1 Ω < rc,max): The voltage ripples are displayed in Fig. 11(b). Owing to the presence of ESR, the total peak-to-peak OVR is increased to 0.07 V. However, this value is smaller than the maximum allowed OVR (0.12 V).

Case 3 (rc = rc,max = 0.2398 Ω): The voltage ripples are shown in Fig. 11(c). The ESR voltage ripples increase further, such that the peak-to-peak OVR reaches 0.12 V, which is equal to the maximum allowed OVR.

Case 4 (rc = 0.4 Ω > rc,max): As shown in Fig. 11(d), the voltage ripples caused by ESR highly increase. The peak-to-peak OVR is 0.19 V, which is greater than the allowed OVR limit (0.12 V). Thus, the desired performance of the buck converter is degraded.

A hardware prototype of buck converter is set up to verify the theoretical studies and simulation results, as shown in Fig. 12. A ferrite core inductor of 490 μH (with 0.5 Ω ESR) and an electrolytic capacitor of 50 μF (with 0.1 Ω ESR) are used. The other key components are listed in Table II. The experimental results are shown in Fig. 13. Fig. 13(a) shows that the output voltage is 11.2 V with a duty cycle of 0.6. If the duty cycle is maintained at 0.642, as obtained from the proposed formula in Equ. (15), then the output voltage is 12 V. Figs. 13(b) and 13(c) show the OVR for rc < rc,max and rc > rc,max , respectively. For rc = 0.1 Ω, the OVR is 75 mV, which is within the maximum specified limit (120 mV). For rc = 0.4 Ω, the OVR is 190 mV, as shown in Fig. 13(c). This value is greater than the maximum specified limit (120 mV). Therefore, the experimental results validate the theoretical and simulation results. The dependency of OVR on switching frequency is also experimentally validated for different values of the capacitor ESR. Fig. 14(a) shows that with rc = 0.1 Ω, the OVR is less than 0.12 V for a frequency greater than 20 kHz. Fig. 14(b) shows that with rc = 0.35 Ω, the OVR is within the specified limit for a frequency above 30 kHz. Similarly, Fig. 14(c) depicts that if the converter operates at a switching frequency greater than or equal to 50 kHz, then the OVR is within the desired limit even with a large ESR value of 0.5 Ω. Hence, if the converter operates at a higher frequency, the OVR may remain within the specified limit even with a higher ESR value. The OVR depends on ESR and converter frequency in an opposite manner.

Fig. 12.Experimental setup for the DC–DC buck converter.

TABLE IIKEY COMPONENT LIST

Fig. 13.Experimental results: (a) output voltage response with ideal and proposed duty cycles, (b) OVR with rc = 0.1 Ω, and (c) OVR with rc= 0.4 Ω.

Fig. 14Experimental results of output voltage variation with frequency with (a) rc = 0.1 Ω, (b) rc = 0.35 Ω, and (c) rc = 0.5 Ω.

 

IV. CONCLUSION

In this study, the duty cycle formula for a non-ideal DC–DC buck converter is improved considering parasitic elements. The effect of these parasitics on inductor and capacitor designs is analyzed. Analyses show a significant difference in inductor and capacitance values with the inclusion of non-ideal components. The ESR of output capacitor contributes significant ripples to output voltage. For specified OVR and switching frequency, the maximum allowable value of this ESR is derived. The simulation and experimental results indicate that an ESR beyond this maximum value results in unwanted OVR. Therefore, this analysis may be interesting and useful for a power electronic engineer to design a high-precision power supply. The proposed analysis, with suitable modifications, can be generalized to design other types of DC–DC converters.