• Title/Summary/Keyword: Output Matching Circuit

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Performance Enhancement of 3-way Doherty Power Amplifier using Gate and Drain bias control (Gate 및 Drain 바이어스 제어를 이용한 3-way Doherty 전력증폭기와 성능개선)

  • Lee, Kwang-Ho;Lee, Suk-Hui;Bang, Sung-Il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.1
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    • pp.77-83
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    • 2011
  • In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

Wideband Class-J Power Amplifier Design Using Internal Matched GaN HEMT (내부정합된 GaN HMET를 이용한 광대역 J-급 전력증폭기 설계)

  • Lim, Eun-Jae;Yoo, Chan-Se;Kim, Do-Gueong;Sun, Jung-Gyu;Yoon, Dong-Hwan;Yoon, Seok-Hui;Rhee, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.2
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    • pp.105-112
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    • 2017
  • In order to satisfy the diffusion of multimedia service in mobile communication and the demand for high-speed communication, it is essential to modify and improve high efficiency, wideband and nonlinear characteristic of multiband power amplifier. This research is designed to implement a single-stub matching circuit as a 2nd harmonic one that meets conditions of the Class-J power amplifier. Low characteristic impedance of the single-stub line is necessary to suit conditions of wideband Class-J. This research uses ceramic substrates having high permittivity to implement the single-stub line with low characteristic impedance, which eventually results in an amplifier satisfying the output impedance terms of Class-J in wideband frequency range. This result attributes to use of GaN HEMT packaged with a 2nd harmonic matching circuit and external fundamental circuit. The measurement results of the Class-J amplifier confirms the following characteristics: more than output power of 50 W(47 dBm) in bandwidth of 1.8~2.7 GHz(0.9GHz), maximum drain efficiency of 72.6 %, and maximum PAE characteristic of 66.5 %.

High-Efficiency CMOS Power Amplifier using Low-Loss PCB Balun with Second Harmonic Impedance Matching (2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기)

  • Kim, Hyungyu;Lim, Wonseob;Kang, Hyunuk;Lee, Wooseok;Oh, Sungjae;Oh, Hansik;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.2
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    • pp.104-110
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    • 2019
  • In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.

Dual-Band Class F Power Amplifier using CRLH-TLs for Multi-Band Antenna System (다중밴드 안테나 시스템을 위한 CRLH 전송선로를 이용한 이중대역 Class F 전력증폭기)

  • Kim, Sun-Young;Seo, Chul-Hun
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.12
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    • pp.7-12
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    • 2008
  • In this paper, a highly efficiency power amplifier is presented for multi-band antenna system. The class F power amplifier operating in dual-band designed with one LDMOSFET. An operating frequency of power amplifier is 900 MHz and 2.14 GHz respectively Matching networks and harmonic control circuits of amplifier are designed by using the unit cell of composite right/left-handed(CRLH) transmission line(TL) realized with lumped elements. The CRLH TL can lead to metamaterial transmission line with the dual-band holing capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of all harmonic components for high efficiency is very difficult, we have controled only the second- and third-harmonics to obtain the high efficiency with the CRLH TL. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency.

Genetic Algorithm Optimization of LNA for Wireless Applications in 2.4GHz Band

  • Kim Ji-Yoon;Yang Doo-Yeong
    • International Journal of Contents
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    • v.2 no.1
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    • pp.29-33
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    • 2006
  • The common-source low noise amplifier(LNA) with inductive degeneration using a genetic algorithm is designed and tested for a down converter in an industrial, scientific and medical (ISM) band application and a wireless broadband internet service (WiBro). The genetic algorithm optimizes the reflection coefficients to be well matched the input and output ports between multistage transistor amplifiers, and it generates low voltage standing wave ratio as well as gain flatness of the amplifier. The stability and the gain flatness of the LNA have been improved by combining the matching circuits and the series feedback microstrip lines with inductive degeneration at common-source port. In the frequency range of ISM band and WiBro application operating at $2.3GHz{\sim}2.5GHz$, the measured power gain and maximum voltage standing wave ratio (VSWR) of the LNA are $41{\pm}0.5dB$ and 1.3, and the noise figure of the LNA is lower than 0.85dB. The above results are agreed well with the theoretical values of the amplifiers.

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Pulsed-Bias Pulsed-RF Passive Load-Pull Measurement of an X-Band GaN HEMT Bare-chip (X-대역 GaN HEMT Bare-Chip 펄스-전압 펄스-RF 수동 로드-풀 측정)

  • Shin, Suk-Woo;Kim, Hyoung-Jong;Choi, Gil-Wong;Choi, Jin-Joo;Lim, Byeong-Ok;Lee, Bok-Hyung
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.10 no.1
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    • pp.42-48
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    • 2011
  • In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

Perfectly-Matched DC Blocks Terminated in Arbitrary Impedances (임의의 종단 임피던스를 갖는 DC Block의 완전 정합)

  • Ahn, Hee-Ran;Kim, Bum-Man
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.895-903
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    • 2007
  • Design equations of DC blocks terminated in arbitrary impedances are newly suggested and a microstrip DC block is tested for the perfect matching. The DC block is a two-port passive component and the power excited at a port is transmitted into another port. However, all the excited power at the input can not be delivered to the output and therefore most of the conventional DC blocks can not be perfectly matched with arbitrary termination impedances. To solve the matching problem, its one-port equivalent resonant circuit model, front which design equations can be derived, is newly suggested. Using the derived design equations, any DC block can be designed, perfectly matched without any restriction of coupling coefficients. To verify the derived design equations, measurements were carried out and the results are in good agreement with prediction, showing insertion and return losses at 4.1 GHz are 0.82dB and -31dB, respectively.

Impedance-matching Method Improving the Performance of the SAW Filter (탄성표면파 필터의 성능 개선을 위한 임피던스 정합의 해석적 방법)

  • 이영진;이승희;노용래
    • The Journal of the Acoustical Society of Korea
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    • v.20 no.5
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    • pp.69-75
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    • 2001
  • In this paper, a fast and easy impedance matching method, which could give the impedance matching component for the general 1 or 2-port network was introduced. First, the entire network structure was defined which consists of the network part to be matched and the impedance matching part composed of inductors and capacitors. Next, the transmission matrix and input and output impedances of the entire network from the terminal impedance conditions were calculated, then the exact solutions for the matching components were obtained. To verify the efficiency of this method, this method was applied to the CDMA If band withdrawal weighted SAW transversal filter, and investigated the effects of the impedance matching before and after, through the simulation and experiment. As the result, the performance of a fractional bandwidth of 1.2%, insertion loss of 29 dB, and VSWR of 80 have improved to a factional bandwidth of 1.8%, insertion loss of 9 dB, VSWR of 3 at 85.38 MHz center frequency. The result shows that this impedance matching method could be used in the SAW devices and other types of 1 or 2-port network.

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Design of A Self-Oscillating Mixer Using A Novel DGS (새로운 DGS구조를 이용한 자기 발진 혼합기 설계)

  • Joung, Myung-Sup;Kim, Jong-Ok;Park, Jun-Seok;Lim, Jae-Bong;Kim, Heong-Seok;Cho, Hong-Goo
    • Proceedings of the KIEE Conference
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    • 2003.07c
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    • pp.1958-1960
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    • 2003
  • Here we describe a unique self-oscillating mixer (SOM) design using a modified defected ground structure (DGS) for down-converter. Proposed SOM is consisted of self-oscillator, which can produce negative resistance and select resonance frequency, and input/output matching filter. As the advantage of this SOM can be reused by module that mix signals with transistor that is used to oscillator, it is simply and low-costly designed Also, there is easy advantage to be applied in RFIC/ MMIC technology because it offers excellent high Q value in spite of using micro-strip structure. Designed self-oscillating frequency is 1.04GHz and RF frequency established is 0.8GHz. It was achieved 20dB conversion loss and phase noise of -95dBc/Hz at 100KHz offset frequency over intermediate frequency (IF). The equivalent circuit parameters for DGS are extracted by using a three dimensional EM simulator and simple circuit analysis method.

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Monolithic Integrated Amplifier for Millimeter Wave Band (밀리미터파 대역 단일 집적 증폭기)

  • Ji, Hong-Gu;Oh, Seung-Hyeub
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.10
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    • pp.3917-3922
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    • 2010
  • In this paper, 3 stage amplifier MMIC was designed and fabricated with U-band optimized epitaxal pHEMT that produced by large signal characterization and modeling for 60 GHz band. The pHEMT used in this paper, the gate $0.12\;{\mu}m$ length and total gate width of $100\;{\mu}m$, $200\;{\mu}m$ has been modeled using the large signal designed with negative feedback and MCLF instead of MIM capacitor for improving stability. Fabricated MMIC $2.5{\times}1.5mm^2$ size, current about 40 mA, operating frequency 59.5~60.5 GHz, gain 19.9~18.6 dB, input matching characteristics -14.6~-14.7 dB, output matching characteristics -11.9~-16.3 dB and output -5 dBm characteristics were obtained.