• Journal of Advanced Navigation Technology
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• v.6 no.4
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• pp.279-290
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• 2002

In this paper, tapered shape of multiport power divider/combiner modified for 2 GHz range from the model published by [10] is proposed. Parameters determining electrical property of the circuit structure have been analyzed by HFSS simulation. For input matching, balance of output signals and phase linearity at each output port, one circular hole has been etched out on the circuit surface. 1:2 and 1:3 power dividers/combiners designed by this study have been compared with the same circuits designed by the method of [10] in terms of S-parameters. As a result, it has been found that the modified structure of power divider/combiner have improved return loss more than 20 dB and another 18 dB, respectively, at 2 GHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of Advanced Navigation Technology
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• v.27 no.6
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• pp.849-854
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• 2023

In this paper, a high-efficiency power amplifier was designed by applying the operating point Class J using LDMOS(laterally diffused metal oxide semiconductor) and optimizing the output matching circuit so that the second harmonic impedance becomes the reactance impedance. The designed power amplifier has a frequency of 108 ~ 110 MHz, Characteristics of PAE(power added efficiency) is 71.5% at P_SAT output (54.5 dBm), 55.5% at P_1dB output (51.5 dBm), and 24.38% at 45 dBm. The CSB(carrier with sideband) amplifier, which is the reference signal in the spatial modulation method, has an operating output of 45 dBm ~ 35 dBm, and linear SDM(sum in the depth of modulation) characteristics(40% ± 0.3%) were obtained. We measure the characteristics in amplitude modulation according to the bias operating point of the power amplifier for CSB and propose the optimal operating point to obtain linear modulation characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.9
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• pp.862-876
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• 1991

In this theses, the procedure for finding the equivalent immittance of an n-line coupled structures is presented in terms of the normal mode parameters of the n-line coupled system. The above generalized equations can be applied to the various Coupled structures including directional couplers, DC blocks, bandpass/band elimination filters, and various other uniformly coupled filters. The design equations are based on a simplified TEM(Quasi TEM) mode. The obtained results and the definition of the scattering parameters for a general coupled line four port with arbitrary terminations are used to present the procedure to determine the optimum physical dimensions matching the given load impedances connected to input, output port. Multiple coupled rnicrostrip two-port with three lines circuit designed shows little discrepancy between the conventional method and this one. Four port with five lines were fabricated on teflon substrate($e$r=2.55) with its thickness h=l.588mm designed at the center frequency, 4 GHz. Their measured results are fairly close to the ones by computation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1069-1077
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• 2011

In this paper, a design and fabrication of a miniaturized 2.5 GHz 8 W power amplifier using selectively anodized aluminum oxide(SAAO) substrate are presented. The process of SAAO substrate is recently proposed and patented by Wavenics Inc. which uses aluminum as wafer. The selected active device is a commercially available GaN HEMT chip of TriQuint company, which is recently released. The optimum impedances for power amplifier design were extracted using the custom tuning jig composed of tunable passive components. The class-F power amplifier are designed based on EM co-simulation of impedance matching circuit. The matching circuit is realized in SAAO substrate. For integration and matching in the small package module, spiral inductors and single layer capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 40 % and harmonic suppression above 30 dBc for the second(2nd) and the third(3rd) harmonic at the output power of 8 W.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.110-114
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• 2008

In this paper, high efficient class F power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. Dual band amplifier is 32.65dBm output power, gain 11dB and PAE 36% at the 2.14GHz, 7dB gain at the 5.2GHz. Design of a dual band class F power amplifier using harmonic control circuit. The measured are 9.9dB gain, 30dBm output power and PAE 55% at the 2.14GHz, 11.7dB gain at the 5.2GHz. This paper is being used the load-pull method and it maximizes output power and it is using the only one transistor in the paper. As a result, this research will obtain a dual band high PAE power amplifier.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1000-1006
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• 2007

This paper presents a power detector circuit which monitors the transmitting power for the application in CDMA cell phones. The proposed power detector are composed of coupler for coupling output power and detector fur monitoring output power. The designed coupler has low loss characteristic because it adopts the stripline structure which consists of two ground planes at both sides of signal plane. The design frequency is 824-849MHz which is the Tx band fur CDMA mobile terminal, and the coupling factor of the stripline coupler is -20dB. A schottky barrier diode is adopted for detector design because of its high speed operation with minimized loss. The required impedance matching is performed to improve the linearity and sensitivity of output voltage at relatively low detector input level where the nonlinear characteristic of diode exists. The package parasitics as well as intrinsic diode model are considered for simulation of the detector. The predicted performances agree well with the measured results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.53-59
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• 2008

In this paper, a novel dual-band high-efficiency class-F power amplifier using the composite right/left-handed (CRLH) transmission lines (TLs) has been realized with one RF Si lateral diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET). The CRLH TL can lead to metamaterial transmission line with the dual-band tuning capability. The dual-band operation of the CRLH TL is achieved by the frequency offset and the nonlinear phase slope of the CRLH TL for the matching network of the power amplifier. Because the control of the all harmonic components is very difficult in dual-band, we have managed only the second- and third-harmonics to obtain the high efficiency with the CRLH TL in dual-band. Also, the proposed power amplifier has been realized by using the harmonic control circuit for not only the output matching network, but also the input matching network for better efficiency. Two operating frequencies are chosen at 880 MHz and 1920 MHz in this work. The measured results show that the output power of 39.83 dBm and 35.17 dBm was obtained at 880 MHz and 1920 MHz, respectively. At this point, we have obtained the power-added efficiency (PAE) of 79.536 % and 44.04 % at two operation frequencies, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.