• Title/Summary/Keyword: Optimal Voltage

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Reactive Reserve Based Contingency Constrained Optimal Power Flow for Enhancement of Voltage Stability Margins (전압안정도 여유 향상을 위한 무효예비력 기반 상정사고 제약 최적조류계산)

  • Song, Hwa-Chang;Lee, Byong-Jun;Kwon, Sae-Hyuk;Ajjarapu, Venkataramana
    • Proceedings of the KIEE Conference
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    • 2003.07a
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    • pp.19-23
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    • 2003
  • This paper presents a new concept of reactive reserve based contingency constrained optimal power flow (RCCOPF) for voltage stability enhancement. This concept is based on the fact that increase in reactive reserves is effective for enhancement of voltage stability margins of post-contingent states, in this paper, the proposed algorithm is applied to voltage stability margin of interface flow. Interface flow limit, in the open access environment, can be a main drawback. RCCOPF for enhancement of interface flow margin is composed of two modules, modified continuation power flow (MCPF) and optimal power flow (OPF). These modules art recursively perform ed until satisfying the required margin of interface flow in the given voltage stability criteria.

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The Schottky Diode of Optimal Stepped Oxide Layer for High Breakdown Voltage (높은 항복전압을 위한 최적 계단산화막의 쇼트키 다이오드)

  • Lee, Yong Jae;Lee, Moon Key;Kim, Bong Ryul
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.4
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    • pp.484-489
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    • 1986
  • A device with variable stepped oxide layer along the edge region of Schottky junction have been designed and fabricated. The effect of this stepped oxide layer in the edge region improves the breakdown voltage as a result of the by increase of the depletion layer width, and decreases the leakage current as compared to the effect of conventional field oxide layer, when the reverse voltage was applied. Experimental results shown that the Schottky diode with the the reverse voltage was applied. Experimenal results show that the Schottky diode with the optimal stepped oxide layer maintains nearly ideal I-V characteristics and excellent breakdown voltage(170V) by reducing the edge effect inherent in metal-semiconductor contacts. The optimal conditions of stepped oxide layer are 1700\ulcornerin thickness and 10\ulcorner in length.

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Optimal Scheduling of Level 5 Electric Vehicle Chargers Based on Voltage Level

  • Sung-Kook Jeon;Dongho Lee
    • Journal of the Korean Society of Industry Convergence
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    • v.26 no.6_1
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    • pp.985-991
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    • 2023
  • This study proposes a solution to the voltage drop in electric vehicle chargers, due to the parasitic resistance and inductance of power cables when the chargers are separated by large distances. A method using multi-level electric vehicle chargers that can output power in stages, without installing an additional energy supply source such as a reactive power compensator or an energy storage system, is proposed. The voltage drop over the power cables, to optimize the charging scheduling, is derived. The obtained voltage drop equation is used to formulate the constraints of the optimization process. To validate the effectiveness of the obtained results, an optimal charging scheduling is performed for each period in a case study based on the assumed charging demands of three connected chargers. From the calculations, the proposed method was found to generate an annual profit of $20,800 for a $12,500 increase in installation costs.

A study on optimal voltage compensation method in west Gyeongnam Power systems (서부경남지역 전력계통의 최적전압 보상에 관한연구)

  • Joung, Yun-Ki;Kim, Seng-Hwan;Yu, In-Keun
    • Proceedings of the KIEE Conference
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    • 2001.07a
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    • pp.164-167
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    • 2001
  • In resent years, electric power quality has become an important issue in power system. Voltage variation and compensation countermeasures of KEPCO system in west Gyeongnam have been simulated using PSS/E. In this paper, in the abnormal power system, the adaption of SVC, high speed and continuous control are simulated for voltage compensation. It is shown that the SVC is the optimal voltage compensation method in loop power system or 2 lines radial system.

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Reducing Power Consumption of a Scheduling Algorithm for Optimal Selection of Supply Voltage under the Time Constraint (시간 제약 조건하에서의 최적 선택 공급 전압을 위한 전력 감소 스케줄링)

  • 최지영;김희석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.11C
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    • pp.1132-1138
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    • 2002
  • This paper proposes a reducing power consumption of a scheduling algorithm for optimal selection of supply voltage. In scheduling of reduction power consumption, we determine the control steps of operations to be executed by exploiting the possibility of using variable voltage levels to reduce power consumption. In the optimal selection of supply voltage binding, we minimize the main factor of the power consumption of the switching activity on the registers using a graph coloring technique. From a set of experiments using high-level benchmark examples, we show that the proposed algorithm prefer to use optimal selection supply voltages rather than uniformed single voltage is effective in reducing power consumption.

On Energy-Optimal Voltage Scheduling for Fixed-Priority Hard Real-Time Systems (고정 우선순위 경성 실시간 시스템에 대한 최적의 전압 스케줄링)

  • 윤한샘;김지홍
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.10
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    • pp.562-574
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    • 2004
  • We address the problem of energy-optimal voltage scheduling for fixed-priority hard real-time systems. First, we prove that the problem is NP-hard. Then, we present a fully polynomial time approximation scheme (FPTAS) for the problem. for any $\varepsilon$>0, the proposed approximation scheme computes a voltage schedule whose energy consumption is at most (1+$\varepsilon$) times that of the optimal voltage schedule. Furthermore, the running time of the proposed approximation scheme is bounded by a polynomial function of the number of input jobs and 1/$\varepsilon$. Experimental results show that the approximation scheme finds more efficient voltage schedules faster than the best existing heuristic.

Optimal Voltage and Reactive Power Scheduling for Saving Electric Charges using Dynamic Programming with a Heuristic Search Approach

  • Jeong, Ki-Seok;Chung, Jong-Duk
    • Journal of Electrical Engineering and Technology
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    • v.11 no.2
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    • pp.329-337
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    • 2016
  • With the increasing deployment of distributed generators in the distribution system, a very large search space is required when dynamic programming (DP) is applied for the optimized dispatch schedules of voltage and reactive power controllers such as on-load tap changers, distributed generators, and shunt capacitors. This study proposes a new optimal voltage and reactive power scheduling method based on dynamic programming with a heuristic searching space reduction approach to reduce the computational burden. This algorithm is designed to determine optimum dispatch schedules based on power system day-ahead scheduling, with new control objectives that consider the reduction of active power losses and maintain the receiving power factor. In this work, to reduce the computational burden, an advanced voltage sensitivity index (AVSI) is adopted to reduce the number of load-flow calculations by estimating bus voltages. Moreover, the accumulated switching operation number up to the current stage is applied prior to the load-flow calculation module. The computational burden can be greatly reduced by using dynamic programming. Case studies were conducted using the IEEE 30-bus test systems and the simulation results indicate that the proposed method is more effective in terms of saving electric charges and improving the voltage profile than loss minimization.

Voltage Quality Improvement with Neural Network-Based Interline Dynamic Voltage Restorer

  • Aali, Seyedreza;Nazarpour, Daryoush
    • Journal of Electrical Engineering and Technology
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    • v.6 no.6
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    • pp.769-775
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    • 2011
  • Custom power devices such as dynamic voltage restorer (DVR) and DSTATCOM are used to improve the power quality in distribution systems. These devices require real power to compensate the deep voltage sag during sufficient time. An interline DVR (IDVR) consists of several DVRs in different feeders. In this paper, a neural network is proposed to control the IDVR performance to achieve optimal mitigation of voltage sags, swell, and unbalance, as well as improvement of dynamic performance. Three multilayer perceptron neural networks are used to identify and regulate the dynamics of the voltage on sensitive load. A backpropagation algorithm trains this type of network. The proposed controller provides optimal mitigation of voltage dynamic. Simulation is carried out by MATLAB/Simulink, demonstrating that the proposed controller has fast response with lower total harmonic distortion.

Optimal Topologies for Cascaded Sub-Multilevel Converters

  • Babaei, Ebrahim
    • Journal of Power Electronics
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    • v.10 no.3
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    • pp.251-261
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    • 2010
  • The general function of a multilevel converter is to synthesize a desired output voltage from several levels of dc voltages as inputs. In order to increase the steps in the output voltage, a new topology is recommended in [1], which benefits from a series connection of sub-multilevel converters. In the procedure described in this reference, despite all the advantages, it is not possible to produce all the steps (odd and even) in the output. In addition, for producing an output voltage with a constant number of steps, there are different configurations with a different number of components. In this paper, the optimal structures for this topology are investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage steps. Two new algorithms for determining the dc voltage sources magnitudes have been proposed. Finally, in order to verify the theoretical issues, simulation and experimental results for a 49-level converter with a maximum output voltage of 200V are presented.

An Analysis of Optimal Link Voltage of VS-SVPWM for Current Harmonics Reduction

  • Lee Dong-Hee;Park Han-Woong;Ahn Jin-Woo;Kwon Young-Ahn
    • Proceedings of the KIPE Conference
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    • 2002.07a
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    • pp.343-346
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    • 2002
  • In recent, complex SVPWM (Space Vector PWM) algorithm can be easily implemented by high performance microprocessor and DSP. Various SVPWM techniques are widely studied due to the advantages of low harmonic distortion and high use ratio of D.C. link voltage. Most of various studies for improving of VS-PWM inverter performance are concentrated about switching pattern and zero pulse pattern split algorithms. However, dc link voltage that is determined at rated load and speed conditions is not proper in the low speed and under rated load. In this paper, analysis of current ripple with digitally implemented SVPWM inverter is introduced according to link voltage. The optimal link voltage in the designed inverter system and load condition is provided in order to suppress output voltage error and current ripple. As remaining the effective voltage vector interval per sampling period sufficiently, additional voltage error and current ripple are suppressed. The proposed algorithm is verified through digital simulation and experimental results.

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