• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.739-741
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• 1993

This paper deals with the Improvement of inverter output waveform with space vector modulation using the DSP-chip. The proposed scheme can be considered as a alternative of the conventional, subharmonic method. This scheme features a maximum output voltage that is 15% greater. The number of switchings is also 30% less than the one obtained by subharmonic modulation method(SHM) A performance function(PF) which is the time integral function of the inverter output voltage is introduced in this paper. An optimal PWM pattern is obtained by minimizing the distortion factor of performance function. The experiment was carried out with an TMS320C25.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.596-599
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• 2003

In this paper, we designed the digital pulse motor control chip including a circular interpolation function. The proposed algorithm in this paper is a nonparametric cure generation algorithm (Jordan's algorith) and a very simple algorithm. So the design for this algorithm used a small number of gates. Also an average error is fairly low. The max output speed is 4Mpps(Pulse per second), the max input frequency is 16MHz and the chip is useful for the stepping and servo motors. The software contains one or two, and many axes linear interpolation algorithm and two axes circular interpolation algorithm.

• 한국정밀공학회지
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• 제7권2호
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• pp.47-57
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• 1990

In-process recognition of the cutting states is one of the very important technologies to increase the reliability of mordern machining process. In this study, practical methods which use the dynamic component of the cutting force are proposed to recognize cutting states (i.e. chip formation, tool wear, surface roughness) in turning process. The signal processing method developed in this study is efficient to measure the maximum amplitude of the dynamic component of cutting force which is closely related to the chip breaking (cut-off frequency : 80-500 Hz) and the approximately natural frequency of cutting tool (5, 000-8, 000 Hz). It can be clarified that the monitoring of the maximum apmlitude in the dynamic component of the cutting force enables the state of chip formation which chips can be easily hancled and the inferiority state of the machined surface to be recognized. The microcomputer in-process tool wear monitor- ing system introduced in this paper can detect the determination of the time to change cutting tool.

• International journal of advanced smart convergence
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• 제11권2호
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2022년도 가을 학술논문 발표대회
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• pp.247-248
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• 2022

The microfluidic controlled droplet production system is one of the most powerful methods for capsule manufacturing. However, stable production is not possible when the powder is included. We solved the above problem by developing an off-chip droplet production system. we checked the droplet creation mechanism and created a simple repair model. It was possible to produce a uniform and stable droplet regardless of the powder content.

• 인터넷정보학회논문지
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• 제25권3호
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• pp.1-8
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• 2024

As the Internet of Things (IoT) has gained significant prominence in our daily lives, most IoT devices rely on over-the-air technology to automatically update firmware or software remotely via the network connection to relieve the burden of manual updates by users. And preserving security for OTA interface is one of the main requirements to defend against potential threats. This paper presents a simulation of an attack scenario on the commoditized System-on-a-chip, ESP32 chip, utilized for drones during their OTA update process. We demonstrate three types of attacks, WiFi cracking, ARP spoofing, and TCP SYN flooding techniques and postpone the OTA update procedure on an ESP32 Drone. As in this scenario, unpatched IoT devices can be vulnerable to a variety of potential threats. Additionally, we review the chip to obtain traces of attacks from a forensics perspective and acquire memory forensic artifacts to indicate the SYN flooding attack.

• 한국통신학회논문지
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• 제26권11B호
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• pp.1546-1555
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• 2001

일반적으로 CDMA 시스템의 해석에서 시스템의 대역폭에 관계없이 한 칩 구간 내에 일정한 평균 전력을 갖는 한 개의 다중 경로 성분만을 고려하고 있다. 그러나 본 논문에서는 고정된 채널 모델에서 시스템의 대역폭에 따라 한 칩 구간 내의 다중 경로 성분들의 수를 달리하고, 이 다중경로 성분들에 자기 상관 함수의 기울기와 상대적인 위상을 고려하여 페이딩의 영향을 해석하였다. 이러한 페이딩이 시스템에 미치는 영향을 알아보기 위해 출력 신호의 통계적 분포를 나타내는 출력 신호의 확률 밀도 함수를 구하였다, 그리고 이 출력 신호에 대한 조건부 에러 확률을 이용하여 사용자 수에 대한 평균 에러 확률을 유도하였다. 광대역 다중 경로 채널 모델로 실측 채널 모델인 JTC 채널 모델을 사용하고, 시스템의 성능 개선을 위해 MRC 레이크 수신기를 사용하였다. 그리고 W-CDMA 시스템의 대역폭에 따른 성능을 공정하게 비교하기 위해 사용자 수를 성능비교의 파라미터로 설정하고 동일한 주파수 대역폭 내에서 hybrid FDMA/CDMA 시스템을 가정하여 비교하였다. 모의 실험의 결과로부터 이용 가능한 많은 다중 경로 성분이 존재할 때 고정된 채널 모델에서 시스템의 분해능이 좋을수록 성능이 우수함을 알 수 있었다.

• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.1-9
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• 2010

삼차원 집적화기술의 현황과 과제 및 향후에 요구되어질 새로운 삼차원 집적화기술의 필요성에 대해 논의를 하였다. Super-chip 기술이라 불리우는 자기조직화 웨이퍼집적화 기술 및 삼차원 헤테로집적화 기술에 대해 소개를 하였다. 액체의 표면장력을 이용하여지지 기반위에 다수의 KGD를 일괄 실장하는 새로운 집적화 기술을 적용하여, KGD만으로 구성된 자기조직화 웨이퍼를 다층으로 적층함으로써 크기가 다른 칩들을 적층하는 것에 성공을 하였다. 또한 삼차원 헤테로집적화 기술을 이용하여 CMOS LSI, MEMS 센서들의 전기소자들과 PD, VC-SEL등의 광학소자 및 micro-fluidic 등의 이종소자들을 삼차원으로 집적하여 시스템화하는데 성공하였다. 이러한 기술은 향후 TSV의 실용화 및 궁극의 3-D IC인 super-chip을 구현하는데 필요한 핵심기술이다.

• Asian Pacific Journal of Cancer Prevention
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• 제14권3호
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• pp.1687-1689
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• 2013

We performed a case-control study to investigate whether SNPs of CHIP might affect the development of IA in Chinese Han nationality. We believe we are the first to have screened IA patients for mutations in the CHIP gene to determine the association with these variants. The study group comprised 224 Chinese Han nationality patients with at least one intracranial aneurysm and 238 unrelated healthy Han nationality controls. Genomic DNA was isolated from blood leukocytes. The entire coding regions of CHIP were genotyped by PCR amplification and DNA sequencing. Differences in genotype and allele frequencies between patients and controls were tested by the chi-square method. Genotype and allele frequencies of the SNP rs116166850 was demonstrated to be in Hardy-Weinberg equilibrium. No significant difference in genotype or allele frequencies between case and control groups was detected at the SNP. Our data do not support the hypothesis of a major role for the CHIP gene in IA development in the Chinese Han population.

• 전자공학회논문지A
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• 제32A권5호
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.