• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.567-574
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• 2003

It is important to design and evaluate the chip waveform with the minimum MAI under the bandwidth constraint in the interference-limited DS-CDMA system. In this paper, by approximation we present the analytical chip waveforms that are proposed and optimized in the reference. Their performances are compared with performances of three conventional chip waveforms: rectangular, half-sine and raised-cosine. Waveform 1 of the proposed chip waveform outperforms the conventional ones. BER and throughput performance are evaluated in the Rayleigh and Nakagami-m fading channels when DPSK modulation is used. When the required BER is 10$\^$-3/ in two fading channels, the capacity of the waveform 1 is improved about 20 % rather than raised-cosine one. When the offered traffic is 30 and the number of packet per bit(N$\sub$d/) is 14, maximum throughput of the waveform 1 is better than raised-cosine chip waveform about 18 % in two fading channels.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.8
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• pp.5195-5200
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• 2014

White LEDs are expected to be applied widely as a lighting system. To make white LED chips, one requires a mixture with silicon and a phosphor coating on a LED blue chip. The process of preparing a mixture with silicon using phosphor involves the use of discarded phosphor in the chip process. Reducing the costs of chip production depends on many factors, such as the mixture errors, exposure over time of silicon, and changes in the characteristics of blue chip. This paper reports the characteristics of a white LED chip manufactured through a reproduction process of derelict phosphor. This method was applicable to a real LED flashlight. A derelict phosphor chip showed similar results to a normal white chip for the degradation of cd 3.2[Cd] and 3.6[Cd], color temperature, 57[K] and 58[K], and maximum white wavelength 444.3[nm] and 449.8[nm]. These results are expected to make ea great contribution to cost reduction.

• KSBB Journal
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• v.20 no.3
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• pp.197-204
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• 2005

Lab-on-a-chip is a miniaturized analytical device in which all of the procedures for the analysis of molecules are carried out, such as pretreatment, reaction, separation, detection, etc. Lab-on-a-chip has increasing concern as a device not only for rapid detection of molecules but also for high throughput screening and point of care, because conventional laborious and time consuming analytical procedures can be substituted. Thus, a lot of microfabrication and analytical techniques for lab-on-a-chip have been developed with microstructures smaller than a few hundreds of micrometers. Separation of the molecules is one of the most important components of lab-on-a-chip, because effective separation method can simplify the design and can provide better sensitivity. The electrokinetic separation based on capillary electrophoresis is most widely employed technique in lab-on-a-chip for the control of fluids and the separation of molecules. In this article, bioseparation techniques and its applications realized in lab-on-a-chip are reviewed.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.17-25
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• 2006

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $moir\'{e}$ interferometry. $Moir\'{e}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for both single and double-sided package assemblies are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one because of its symmetric structure. The largest effective strain occurred at the solder ball located on the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one by 50%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.308-313
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented during down end-milling of Inconel 715 using measure cutting forces. Contrary to the up-end milling the value of radial specific cutting resistance, $K_r$, becomes larger as the helix angle increases from $30^{\circ}$ to $40^{\circ}$ and it shows almost same value at $50^{\circ}$ The value of tangential specific cutting resistance, $K_t$ becomes larger as the helix angle increases same as in up-end milling, the $KK_r$, and $K_t$ values show a tendency to decrease with increase of the modified chip section area and this tendency is distinct with helix angle $40^{\circ}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.89-99
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• 1995

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

• Journal of the Korean Wood Science and Technology
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• v.16 no.4
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• pp.54-60
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• 1988

Machinabilities means inherent properties of pinus densiflora at Chunyang district to be CNC machined easily or not, and processing abilities of the tool and machine together. This explanation signifies that machinabilities have two phases of signification, depended on considering and stress either materials or tools preferentially. This paper discuss machinabilities, the following items are usually employed as the indices of stress distribution at the cutting tool rake face. The stress distributions on the chip - tool contact surface at the early stage of the chip forming and under the stage of fringe pattern in wood cutting were analyzed the photoelastic method. The tool used in the present experiment was the special cutting tool H.S.S. one made in laboratory. And isochromatic fringe pattern and isolinic line of work piece by chip-behavior during the cutting operation were photographed with the feed camera continuously. The effects on the stress, distribution on the rake face of the epoxy tool and the strain distribution in the work piece of wood plate by chip behavior are cleared in pre cent experiment.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.6
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• pp.5-11
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• 2003

The number of the enterprises which utilize network technology has been increasing for solving problems such as productivity improvement, market trend analysis, and material collection for making decision. Especially, the management of equipment and the recovery time reduction when machines break down are very important factors in productivity improvement of the enterprise. Currently, most of the remote trouble diagnosis of equipment using the internet have just one function of transmitting the trouble information to the user. Therefore it does not directly reflect the user's recovery experience or the developer's new recovery methods. If the user's experienced recovery methods or the developer's recovery methods as well as the basic recovery methods are reflected online or on the internet, it makes it possible to recover faster than before. In this paper, we develop a Remote Monitoring Server (RMS) for chip mounters, and make it possible to reduce the recovery time by reflecting the user's experience and developer's new methods in addition to presenting the basic recovery methods. For this, trouble recovery concept will be defined. Based on this, many functions(trouble diagnosis, the presentation of the basic recovery methods, user's and developer's recovery method, counting function of the trouble number of each code, and presentation of usage number of each recovery methods) were developed. By utilizing the reports of the actual results of chip mounter and the notice function of the parts change time, the rate of operation of the chip mounter can be improved.