• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4B
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• pp.245-257
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• 2012

As one of the most challenging tasks in designing the Internet routers, packet classification is required to achieve the wire-speed processing for every incoming packet. Packet classification algorithm which applies binary search on trie levels to the area-based quad-trie is an efficient algorithm. However, it has a problem of unnecessary access to a hash table, even when there is no node in the corresponding level of the trie. In order to avoid the unnecessary off-chip memory access, we proposed an algorithm using Bloom filters along with the binary search on levels to multiple disjoint tries. For ACL, FW, IPC sets with about 1000, 5000, and 10000 rules, performance evaluation result shows that the search performance is improved by 21 to 33 percent by adding Bloom filters.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.1-12
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• 1999

In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.40-47
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• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of Radiation Protection and Research
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• v.16 no.2
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• pp.1-6
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• 1991

The $HgI_2$ single crystal which can be used for the ${\gamma}-ray$ detector at room temperature was grown by Temperature Oscillation Method. The low temperature photoluminescence, specific resistivity and trap concentration of $HgI_2$ single crystal were investigated. Three main luminescence bands were observed at 2.30eV, 2.20eV and 2.00eV at 20K, related to the excitons, I-vacancies and impurities, respectively. The specific resistivity and trap concentration of $HgI_2$ single crystal were $10^{11}{\Omega}\;cm\;and\;1.8{\times}10^{14}/cm^3$ at room temperature, respectively. Also the radiation detecting system was deviced by $HgI_2$ ${\gamma}-ray$ detector, one chip microprocessor, LCD module and personal computer. The prepared $HgI_2$ ${\gamma}-ray$ detector showed a good linearity of ${\gamma}-radiation$ dose for standard ${\gamma}-ray$.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of Biomedical Engineering Research
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• v.21 no.3 s.61
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• pp.255-260
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• 2000

This paper presents a radio-telemetry patient monitor. which is used for intensive cal?e units. emergency and surgical operation rooms to monitor continuously patients' vital signs. The radio-telemetry patient monitor consists of a vital sign acquisition unit. wireless data transmission units and a vital sign-monitoring unit. The vital sign acquisition unit amplifies biological signals, performs analog signal to serial digital data conversion using the one chip micro-controller. The converted digital data is modulated FSK in UHF band using low output power and transmitted to a remote site in door. In comparison with analog modulation. FSK has major advantages to improve performance with respect to noise resistance with fower error and the potential ability to process and Improve quality of the received data. The vital sign-monitoring unit consists of the receiver to demodulate the modulated digital data, the LCD monitor to display vital signs continuously and the thermal head printer to record a signal.

• Archives of design research
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• v.15 no.3
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• pp.29-38
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• 2002

Recently, types of mobile services are ever-growing with technological advances, such as CDMA 2000, 256 Color LCD, 16 channel sound chip set and easy internet access. However, manual system that is supposed to support users for finding features and functions doesn't help users most of the cases since users are moving. Therefore, mobile sonics needs new concept for manual system that can support users while they are in use In this research report, new concept for interactive manual system is suggested. Then a guideline for interactive manual system is developed as a result from three empirical studies. First, ten information visualization methods used for describing functions are positioned on user's perception map. Secondly, user behavior pattern of getting required information from written manual was analyzed. Finally, visual cue system was selected as one of options for developing interactive manual system and a guideline was developed based on these research results.

• Journal of Sensor Science and Technology
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• v.19 no.6
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• pp.456-461
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• 2010

The detection of C-reactive protein(CRP) using self-assembled monolayer(SAM) was investigated by a portable surface plasmon resonance(SPR) sensor system. The CRP is a biomarker for the possible cardiovascular disease. The SAM was formed on gold(Au) surface to anchor the monoclonal antibody of CRP(anti-CRP) for detection of CRP. Sequence injection of the anti-CRP and bovine serum albumin(BSA) into the sensor system has been carried out immobilize the antibody and to prevent non-specific binding. The portable SPR system has two flow channels: one for the sample measurements and the other for the reference. The output SPR signal was increased with the injection of the anti-CRP, BSA and CRP due to binding of the proteins on the sensor chip. The valid output SPR signals was linearly related to the critical range of the CRP concentration. The experimental results showed the feasibility of the portable SPR system with newly developed SAM to diagnose a risk of the future cardiovascular events.