• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.30-36
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• 1990

Context-free language can be recognized by Cocke-Younger-Kasami algorithm. This algorithm is a class of polyadic-nonserial dynamic programming technique and has the O(n**3) time complexity. In this paper, a one-dimensional systolic array for recognition of context-free language is designed. The designed triangle type two-dimensional array is projected and transformed to an one-dimensional array. The designed one-dimensional array has n processing elements and \ulcornern+1)/2\ulcorner(n-1)+3n-1 time units to process the algorithm (n is the length of input string). The time complexity is O(n\ulcorner.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10b
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• pp.782-785
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• 1988

A two-dimensional positioning system by use of an M-array is proposed. An M-array pattern, which is known as one of the two-dimensional pseudorandom array, is attached on an object to be positioned. The M-array pattern is observed by a TV camera and crosscorrelated with the reference M-array. The maximum of the two-dimensional crosscorrelation function is sought by two-dimensional servo system. This method of positioning can be used in very noisy circumstances.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.708-714
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• 2000

In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

• Korean Journal of Materials Research
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• v.13 no.11
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• pp.708-710
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• 2003

One-dimensional array of InAs quantum dots (QDs) have been grown on V-grooved GaAs substrates by low-pressure metalorganic chemical vapor deposition. Atomic force microscope images show that InAs QDs are aligned in one-dimensional rows along the ［011］oriented bottom of V-grooves and no QDs are formed on the sidewalls and the surface of mesa top. Capability to grow one-dimensional InAs QDs array would feasible for the single electron tunneling devices and other novel quantum-confined devices.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.4
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• pp.1.1-11
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• 1974

A general and systematic method of organizing two-dimensional flexible cellular array which is capable of reclizing arbitrary combinational switching function is developed. A set of n functions of n variables is transformed to revalued functions of one variable. This set of functions form a semigroup under the normal operation which is defined in this paper. A systematic method of generating any functions using three base functions is presented. Three basic networks which are capable of realizing three base functions are designed using only one one-dimensional array. The algorithm is presented for lealizing arbitrary combinational switching functions by organizing this basic array in two.dimensional cellular array and by appropriately setting the parameters or the edge of the array.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• Journal of applied mathematics & informatics
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• v.42 no.3
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• pp.483-497
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• 2024

Isometric array grammar is one of the simplest model to generate picture languages, since both sides of its production rule have the same shape. In this paper, we have introduced isometric fuzzy regular array grammars to generate isometric fuzzy regular array languages and discussed its closure properties. Also, the relation between isometric fuzzy regular array grammar and boustrophedon fuzzy finite automata has been discussed. Moreover, we study the relation between two dimensional fuzzy regular grammars with returning fuzzy finite automata and boustrophedon fuzzy finite automata. Further, the hierarchy results of these three classes of languages have been discussed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.4
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• pp.514-522
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• 2000

In this thesis, a two-dimensional active phased array antenna without phase shifter is studied for two-dimensional beam scanning. A designed two-dimensional oscillator-type active array antenna, radiation elements and the oscillator circuits were combined with via-hole and coupled by slot on the opposite ground plane. The operating characteristics are analyzed and experimentally demonstrated , The two-dimensional $4\times4$ elements were designed for the proper coupling strengths and coupling phases by adjusting the width, length and offset position of slot-lines. The fabricated active phased array antenna shows the beam shift characteristics capable of scanning from $-17^{\circ}$ to $18^{\circ}$ with respect to broadside in one dimension, from $-5^{\circ}$ to $10^{\circ}$ in two dimension. The experimental results show that it is possible to use the oscillator-type active phased array antenna as a two-dimensional planar array antenna.