• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• ETRI Journal
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• v.37 no.3
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• pp.523-532
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• 2015

Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are $28.3{\mu}m$, $31.7{\mu}m$, and $26.3{\mu}m$, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.

• Journal of the Korea Society of Computer and Information
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• v.18 no.6
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• pp.1-8
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• 2013

In this paper, we design and implement a firmware for low-cost small PCR devices. To minimize machine code size, the proposed firmware controls real-time tasks simultaneously only with support of the hardware interrupt, but without support of the operating system program. The proposed firmware has the host-local structure in which the firmware receives operation commands from PC and sends operation results to PC through usb communication. We implement a low-cost small PCR device with the proposed firmware loaded on microchip PIC18F4550 chip, and verify that the implemented PCR device significantly reduces cost and volume size of existing commercial PCR devices with a similar performance.

• Journal of Hydrogen and New Energy
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• v.16 no.3
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• pp.238-243
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• 2005

Mg and Mg-based alloys are most important hydrogen storage materials. It is a lightweight and low-cost materials with high hydrogen storage capacity. However, the formation of hydride at high temperature, the deterioration effect, the hydriding and dehydriding kinetics are bad factor for application. In this study, Mg and Ni have been produced by hydrogen induced mechanical alloying(HIMA) process. The raw materials, Mg(purity 99.9%) chip and Ni(purity 99.95%) chip was prepared by using a planetary ball mill apparatus(FRITSCH pulverisette 5). The balls to chips mass ratio(BCR) are 30:1. The hydrogen pressure induced 2.0MPa and milling times were 12, 24, 48, 72, 96 hours with a rotating speed of 200rpm. X-ray diffraction(XRD) analysis was made to characterize the crystallite size and misfit strain. The crystallite size measured by laser particle size analysis(PSA). Microstructure changes were investigated by scanning electron microscopy(SEM) and the transmission electron microscopy(TEM). The hydrogen storage properties were evaluated by using an Sivert's type automatic pressure-composition-therm(PCT) apparatus.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.96-104
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• 2007

In this paper, the field solver based deembedding technique for the on-chip inductors to deembed the pad and surrounding ground effect was described, and the results from field solver based deembedding techniques and measurement based matrix calculation method were compared. In addition, LNA circuit is designed by using deembedded inductors and fabricated by using standard $0.25{\mu}m$ CMOS process, in the range over the 2.5GHz it shows the good agreements between measurement and simulation results when the proper deembedding was adapted. Supposed deembedding techniques can be used to get the pure on-chip devices's values and adapted to design accurate RFIC circuit design.

• ETRI Journal
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• v.29 no.3
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• pp.371-380
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• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.104-108
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• 2000

In this paper, we characterized a novel MEMS package using high resistivity silicon for microwave and millimeter-wave devices. The manufactured MEMS package shows -20dB of S$\sub$11/ and -0.4dB of S$\sub$21/ up to 200GHz. The new package can be a low cost and high performance solution due to process compatibility with on-chip devices and very small and precise dimensions by semiconduotor technology.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.514-520
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• 2002

In this paper, the study of a design and fabrication of the receiver MMIC mixer for L-band application is described. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The conversion gain of the mixer is -14 dB, IIP3 is approximately 4 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.4\;mm{\times}1.4\;mm$.