• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.563-566
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• 2003

We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.

• 한국ITS학회 논문지
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• 제11권4호
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• pp.63-69
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• 2012

본 논문에서는 용량성 지문센서의 회색조 이미지를 얻기 위한 새로운 회로를 제안하고 있다. 기존의 회로는 회색조 이미지를 얻기 위해 많은 칩 면적을 차지하는 DAC를 적용하거나 전력소모가 많고 전역 클럭을 적용하는 비휘발성 메모리에 적용되는 승압회로를 픽셀별로 적용하였다. 개선된 전하분할 방식의 용량성 지문센서 감지회로는 뉴런모스(vMOS) 기반의 DLC(down literal circuit) 회로와 단순화된 아날로그 MUX(multiplexor)를 적용하였다. 설계된 감지회로는 0.3V, $0.35{\mu}m$ CMOS공정을 적용하여 동작을 검증하였다. 제안된 회로는 기존의 비교기와 주변회로를 필요로하지 않으므로 단위 픽셀의 레이아웃 면적을 줄이고 이미지의 해상도를 향상 시킬 수 있다.

• 한국정보통신학회논문지
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• 제20권9호
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• pp.1747-1754
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• 2016

본 논문에서는 고정밀 하이브리드 온 칩 온도센서를 제안하였다. 제안된 온도센서에서는 SAR 타입 온도센서와 ${\Sigma}{\Delta}$타입 온도센서를 혼합하였다. SAR 타입 온도센서는 ${\Sigma}{\Delta}$타입 온도센서 보다 온도를 찾아가는 속도가 빠르지만 오차가 발생할 확률이 높은 단점이 있고, ${\Sigma}{\Delta}$ 타입 온도센서는 SAR 타입 온도센서 보다 정확하지만 속도가 느린 단점이 있다. 제안된 온도 센서는 두개의 온도 측정방법을 혼합하여 고정밀 고속 온도측정이 가능하다. 또한, 칩 제작 후 온도 오차 값을 메모리회로에 저장하여 온도 오차를 보상하는 회로를 포함하여 온도센서를 구현하였다. 제안된 온도센서는 $0.35{\mu}m$ CMOS 공정으로 제작되었다. 온도 정확도, 소비 전력, 칩 면적은 각각 $0.15^{\circ}C$, $540{\mu}W$, $1.2mm^2$였다.

• 한국정보과학회논문지:시스템및이론
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• 제37권5호
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• pp.292-303
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• 2010

온칩(on-chip) 캐쉬는 외부 메모리로의 접근을 감소시키며 빈번하게 접근되기 때문에 내장형 시스템의 성능과 에너지 소비 측면에서 중요한 역할을 한다. 본 논문에서는 내장형 시스템에 맞추어 설계된 2-레벨 데이터 캐쉬 메모리 구조를 제안하고자 한다. 레벨1(L1) 캐쉬의 구성으로 작은 크기, 직접시장(direct-mapped) 그리고 바로쓰기(write-through)를 채용한다. 대조적으로 레벨2(L2) 캐쉬는 보통의 캐쉬 크기와 집합연관(set-associativity) 그리고 나중쓰기(write-back) 정책을 채용한다. 결과적으로 L1 캐쉬는 빠른 접근 시간을 가지며 (한 사이클 이내) L2 캐쉬는 전체 캐쉬의 미스율(global miss rate)을 낮추는데 효과적이다. 작은 크기의 L1 데이터 캐쉬로 인한 증가된 캐쉬 미스율(miss rate)을 줄이기 위해 ECP(Early Cache hit Predictor)기법을 제안하였다. 제안된 ECP기법은 L1 캐쉬 히트 예측을 통해서 요청된 데이터가 L1 캐쉬에 있는지 예측할 수 있으며 추가적으로, ALU를 필요로 하지 않고 빠르게 유효주소(effective address)계산을 할 수 있다. 또한, 두 캐쉬 계층간 바로쓰기(write-through) 정책에서 오는 빈번한 L2 캐쉬 접근으로 인한 에너지 소비를 줄이기 위해 지정웨이 쓰기(one-way write) 기법을 제안하였다. 제안된 지정웨이 쓰기 기법을 이용하면 바로쓰기 정책으로 인한 L1 캐쉬에서 L2 캐쉬로의 쓰기 접근시 태그(tag) 비교 과정을 거치지 않고 하나의 지정된 웨이를 바로 접근할 수 있다. 사이클 단위 정확도의 시뮬레이터와 내장형 벤치마크를 이용한 실험 결과 본 논문에서 제안한 2-레벨 데이터 캐쉬 메모리 구조는 평균적으로 3.6%의 성능향상과 50%의 데이터 캐쉬 에너지 소비를 감소 시켰다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.9-9
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• 2011

The transfer of nano-science accomplishments into technology is severely hindered by a lack of understanding of barriers to nanoscale manufacturing. The NSF Center for High-rate Nanomanufacturing (CHN) is developing tools and processes to conduct fast massive directed assembly of nanoscale elements by controlling the forces required to assemble, detach, and transfer nanoelements at high rates and over large areas. The center has developed templates with nanofeatures to direct the assembly of carbon nanotubes and nanoparticles (down to 10 nm) into nanoscale trenches in a short time (in seconds) and over a large area (measured in inches). The center has demonstrated that nanotemplates can be used to pattern conducting polymers and that the patterned polymer can be transferred onto a second polymer substrate. Recently, a fast and highly scalable process for fabricating interconnects from CMOS and other types of interconnects has been developed using metallic nanoparticles. The particles are precisely assembled into the vias from the suspension and then fused in a room temperature process creating nanoscale interconnect. The center has many applications where the technology has been demonstrated. For example, the nonvolatile memory switches using (SWNTs) or molecules assembled on a wafer level. A new biosensor chip (0.02 $mm^2$) capable of detecting multiple biomarkers simultaneously and can be in vitro and in vivo with a detection limit that's 200 times lower than current technology. The center has developed the fundamental science and engineering platform necessary to manufacture a wide array of applications ranging from electronics, energy, and materials to biotechnology.

• 대한기계학회논문집B
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• 제27권11호
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• pp.1637-1644
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• 2003

Stereoscopic particle image velocimetry is a measurement technique to acquire three dimensional velocity field by two cameras. With a laser sheet illumination, the third velocity component can be deduced from out-of$.$plane velocity components using a stereoscopic matching method. Most industrial fluid flows are three dimensional turbulent flows, so it is necessary to use the stereoscopic PIV measurement method. However the existing stereoscopic PIV system seems hard to use since it is very expensive and complex. In this study we have developed a Miniature Stereo-PIV(MSPIV) system based on the concept of the Miniature PIV system which we have already developed. In this paper, we address the design and some primitive experimental results of the Miniature Stereo-PIV system. The Miniature Stereo-PIV system features relatively modest performances, but is considerably smaller, cheaper and easy to handle. The proposed Miniature Stereo-PIV system uses two one-chip-only CMOS cameras with digital output. Only two other chips are needed, one for a buffer memory and one for an interfacing logic that controls the system. Images are transferred to a personal computer (PC) via its standard parallel port. No extra hardware is required (in particular, no frame grabber board is needed).

• 센서학회지
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• 제15권5호
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• pp.334-340
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• 2006

A compact biosignal monitoring device was developed. Electrodes for electrocardiogram (ECG) and a LED and silicon detector for photoplethysmogram (PPG) were used. A lead II type was arranged for ECG measurement and reflected light was measured at the finger tip for PPG. A single chip microprocessor (model ADuC812, Analog Device) controlled a measurement protocol and processed measured signals. PPG and ECG had a sampling rate of 300 Hz with 8-bit resolution. The maximum power consumption was 100 mW. The microprocessor computed pulse transit time (PTT) between the R-wave of ECG and the peak of PPG. To increase the resolution of PTT, analog peak detectors obtained the peaks of ECG and PPG whose interval was calculated using an internal clock cycle of 921.6 kHz. The device was designed to be operated by 3-volt battery. Biosignals can be measured for $2{\sim}3$ days continuously without the external interruptions and data is stored to an on-board memory. Our system was successfully tested with human subjects.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2002년도 학술대회지
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• pp.517-520
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• 2002

Stereoscopic particle image velocimetry is a measurement technique to acquire of three dimensional velocity field by two cameras. With a laser sheet illumination, the third velocity component can be deduced by out-of-plane velocity components using a stereoscopic matching method. Industrial fluid flows are almost three dimensional turbulent flows, so it is necessary to use the stereoscopic PIV measurement method. However the existing stereoscopic PIV system seems hard to use since it is very expensive and complex. In this study we have developed a Stereoscopic Miniature PIV(MPIV) system based on the concept of the Miniature PIV system which we have already developed. In this paper, we address the design and some first experimental results of the stereoscopic PIV system. The Stereoscopic MPIV system features relatively modest performances, but is considerably smaller, cheaper and easy to handle. The proposed Stereoscopic MPIV system uses two one-chip-only CMOS cameras with digital output. Only two other chips are needed, one for a buffer memory and one for an interfacing logic that controls the system. Images are transferred to a personal computer (PC) via its standard parallel port. No extra hardware is required (in particular, no frame grabber board is needed).

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.535-544
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• 2008

Unlike MS(Magnetic Stripe), SMART CARD is equipped with COS(Chip Operating System) consisting of the Microprocessor and Memory where information can be stored and processed, and there are two types of cards according to the contact mode; the contact type that passes through a gold plated area and the contactless one that goes through the radio-frequency using an antenna embedded in the plastic card. the contactless IC card used for the transportation card was first introduced into local area buses in Seoul, and expanded throughout the country so that it has removed the inconvenience such as possession of cash, fare payment and collection. Focusing on the Seoul metropolitan area in 2004, prepaid and pay later cards were adopted and have been used interchangeably between a bus and subway. The card terminal compatible between a bus and subway is Proximity Integrated Circuit Card(PICC) as international standards(1443 Type A,B), communicates in the 13.56MHz dynamic frequency modulation-demodulation system, and adopts the Multi Secure Application Module(SAM). In the second half of 2009, the system avaliable nationwide will be built when the payment SAM standard is implemented.