• Microbiology and Biotechnology Letters
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• v.25 no.6
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• pp.537-545
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• 1997

The aim of the present research program was to isolate a strain of actinomycetes producing antifungal substance. Soil samples were collected from various sites in Korea and a number of actinomycetes were isolated from the soil samples by applying selective agar for actinomycetes. Among isolates, a strain (NA -52) producing antifungal substance against Pyricularia oryzae was selected. Chemotaxonomic and numerical identification were carried out for the isolate. Fifty taxonomic unit characters were tested and the data were analyzed numerically using TAXON program. The isolate was identified as a synonym of streptomyces diastaticus belong to cluster No. 19 (Streptomyces diastaticus). But it showed a low similarity to S. diastaticus in simple matching coefficients, hence it was considered as one new species in Streptomyces.

• Journal of the Korean Society for information Management
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• v.17 no.1
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• pp.21-47
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• 2000

Keeping the semantic interoperability between different formats is very important for reuseing and consistently processing metadata. This article is to design common schema and KORMARC schema based on RDF schema. For this, common elements are made by comparison of Dublin Core elements and KORMARC fields. The schema of these elements is designed for construction of semantic interoperability, basing RDF schema specification and syntax specification. Eventually, the semantic interoperability between a number of metadata formats can be constructed by matching the common elements to each attribute of format. KORMARC schema is designed by the application of common schema.

• IE interfaces
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• v.10 no.1
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• pp.47-55
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• 1997

This paper deals with an assembly process of the TFT glasses and the color filters in LCD manufacturing. Two specific problems are presented and solved. One is a matching problem to find the best matches between a set of TFT glasses and a set of color filters, which result in the maximum number of good LCD assemblies. A simple mathematical model is constructed for this problem and an optimal solution can be obtained using an existing algorithm. The other is a main problem that requires a determination of an economic lot size of the color filters which are going to be assembled with a given set of TFT glasses. A Bayesian dynamic forecasting model is developed to predict the defective patterns of color filters. Based on the predicted defective rate of color filters, the minimum lot size of the color filters can be determined to minimize the probability of losing good TFT glasses and color filters.

• Journal of Biosystems Engineering
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• v.23 no.4
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• pp.373-380
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• 1998

The contribution of this paper is to provide the methods for the production automation of potato microtuber using the vision process in growth monitoring. The first method deals with computation for the growth density in the primary growth process. The second method addresses cognition process to identify the number and the volume of potato microtuber in secondary growth process. The third is to decide whether potato microtubers are infected by a virus or bacteria in growth process. The computation for the growth density in the primary growth process uses the method of Labeling. The second and third methods use template matching based on color patterns. With the developed method using vision process, this experiment is capable of discriminating weekly growth-rate in primary growth process, 85% cognition rate in secondary process and identifying whether there are infections. Therefore, we conclude that our experimental results are capable of growth monitoring for mass production of potato microtubers.

• Proceedings of the KOSOMBE Conference
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• v.1990 no.05
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• pp.21-24
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• 1990

This paper presents a new algorithm for P-wave detection in the ECG signal, we get the peak, onset and offset point by using significant point extraction algorithm with 5-point derivative. To these set of extracted significant points, we apply amplitude and duration threshold criterion. we define the set of significant point meeting the criterion as P-wave candidate. Then P-wave candidate is classified through match-process with template. The template with maximum number or P-wave candidate is selected to be the P-wave.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.316-321
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• 2000

In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

• Journal of Information Processing Systems
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• v.7 no.3
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• pp.425-434
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• 2011

The success of iris recognition depends mainly on two factors: image acquisition and an iris recognition algorithm. In this study, we present a system that considers both factors and focuses on the latter. The proposed algorithm aims to find out the most efficient wavelet family and its coefficients for encoding the iris template of the experiment samples. The algorithm implemented in software performs segmentation, normalization, feature encoding, data storage, and matching. By using the Haar and Biorthogonal wavelet families at various levels feature encoding is performed by decomposing the normalized iris image. The vertical coefficient is encoded into the iris template and is stored in the database. The performance of the system is evaluated by using the number of degrees of freedom, False Reject Rate (FRR), False Accept Rate (FAR), and Equal Error Rate (EER) and the metrics show that the proposed algorithm can be employed for an iris recognition system.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.717-720
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• 1998

In this paper, we propose a VLSI architecture for implementing a crecently proposed fast block matching algorithm, which is called the HSBMA3S. The proposed architecture consists of a systolic array based basic unit and two shift register arrays. And it covers a search range of -32 ~+31. By using a basic unit repeatedly, we can redcue the number of gates. To implement the basic unit, we can select one among various conventional systolic arrays by trading-off between speed and hardware cost. In this paper, the architecture for the basic unit is selected so that the hardware cost can be minimized. The proposed architecture is fast enough for low bit-rate applications (frame size of 352x288, 30 frames/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic unit, the architecture can be used for the higher bit-rate application of the frame size of 720*480 and 30 frames/sec.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Journal of IKEEE
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• v.21 no.2
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• pp.130-135
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• 2017

Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.