• Journal of Microbiology and Biotechnology
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• v.9 no.3
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• pp.340-345
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• 1999

A novel simultaneous saccharification and fermentation (SSF) process from the microcrystalline cellulose to ethanol was developed by using $\delta$-integrated recombinant cellulolytic Saccharomyces cerevisiae L2612$L2612\deltaGC$, which can utilize cellulose as carbon and energy sources. The optimum amount of enzymes needed for the efficient conversion of cellulose to ethanol at $30^{\circ}C$ was determined with commercial cellulolytic enzymes. By fed-batch cultivation, the heterologous cellulolytic enzymes were accumulated up to 42.67% of the total cellulase and 29% of the $\beta$-glucosidase needed for the efficient SSF process. When this $\delta$-integrated recombinant yeast was applied to the successive SSF step for ethanol production, 20.35 g/l of ethanol was produced after 12 h from 50 g/l of microcrystalline cellulose. By using this novel SSF process, a considerable amount of commercial enzymes was reduced.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Clean Technology
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• v.9 no.3
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• pp.101-105
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• 2003

Plasma etching technology has been developed since it is recognized that silicon etching is very crucial in MEMS(Micro Electro Mechanical System) technology. In this study ICP(Inductive Coupled Plasma) technology was used as a new plasma etching to increase ion density without increasing ion energy, and to maintain the etching directions. This plasma etching can be used for many MEMS applications, but it has been used for PCR(Polymerase Chain Reaction) device fabrication. Platen power, Coil power and process pressure were parameters for observing the etching rate changes. Conclusively Platen power 12W, Coil power 500W, etchng/passivation cycle 6/7sec gives the etching rate of $1.2{\mu}m/min$ and sidewall profile of $90{\pm}0.7^{\circ}$, exclusively. It was concluded from this study that it was possible to minimize the environmental effect by optimizing the etching process using SF6 gas.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.55-59
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• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

• Structural Engineering and Mechanics
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• v.75 no.6
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• pp.771-784
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• 2020

Reliability analysis techniques combining with various surrogate models have attracted increasing attention because of their accuracy and great efficiency. However, they primarily focus on the structures with continuous response, while very rare researches on the reliability analysis for structures with discontinuous response are carried out. Furthermore, existing adaptive reliability analysis methods based on importance sampling (IS) still have some intractable defects when dealing with small failure probability, and there is no related research on reliability analysis for structures involving discontinuous response and small failure probability. Therefore, this paper proposes a novel reliability analysis method called AGPC-IS for such structures, which combines adaptive Gaussian process classification (GPC) and adaptive-kernel-density-estimation-based IS. In AGPC-IS, an efficient adaptive strategy for design of experiments (DoE), taking into consideration the classification uncertainty, the sampling uniformity and the regional classification accuracy improvement, is developed with the purpose of improving the accuracy of Gaussian process classifier. The adaptive kernel density estimation is introduced for constructing the quasi-optimal density function of IS. In addition, a novel and more precise stopping criterion is also developed from the perspective of the stability of failure probability estimation. The efficiency, superiority and practicability of AGPC-IS are verified by three examples.

• Proceedings of the Korea Technical Association of the Pulp and Paper Industry Conference
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• 2002.05a
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• pp.34-45
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• 2002

The new measuring method of micro-stickies considering both the effects of charge neutralization and evaporation of process water was developed by KRICT PPRC. By the new KRICT method, the contamination of metal dryer surface and other machine clothes could be estimated quickly and simultaneously. According to this study, it could be confirmed that the novel method is a useful one for the evaluation of several treatments regarding the reduction of stickies troubles.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.4008-4022
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• 2016

This paper tries to extend the conventional conceptual framework of the Internet of Things (IoT) so as to reify an advanced pervasive IoT-community collaboration concept, which is called the process-aware Internet of Things. The extended conceptual framework is embodied as a referential architecture that can be a standardized reference model supporting the conceptual integration of the Internet of Things and the process awareness. The extended referential architecture covers the full range of the architectural details from abstracting the process-aware behavioral semantics to reifying the IoT-process enactments. These extended framework and architecture ought to be the theoretical basis for implementing a process-aware IoT-community computing system supporting process-aware collaborations of Things in pervasive computing environments. In particular, we do point up that the proposed framework of the process-aware Internet of Things is revised from the Internet of Things framework announced in ITU-T SG13³ Y.2060 [26] by integrating the novel concept of process awareness. We strongly believe that the extended conceptual framework and its referential architecture are able to deliver the novel and meaningful insight as a standardized platform for describing and achieving the goals of IoT-communities and societies.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.245-250
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• 1998

Novel fabrication process of vertical spring for micro mirror array is proposed. The proposed fabrication process adopts a shadow evaporation process using shielding screen structure on top of the sacrificial layer. The 50${\times}$50 micro mirror arrays are fabricated using the proposed process and ceramic packaged. The static and dynamic characteristics of mirror are measured. The mirror plate touches substrate at 16V and the response time of about 16.8 ${\mu}\textrm{s}$. The resonant frequency of mirror is 16kHz. The spring thickness is calculated from static characteristic to be 1075${\AA}$.

• ETRI Journal
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• v.31 no.6
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• pp.778-783
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• 2009

To fabricate uniform and reliable thin gold stripes that provide low-loss optical waveguides, we developed a novel liftoff process placing an additional $SiN_x$ layer under conventional photoresists. By patterning a photoresist and over-etching the $SiN_x$, the photoresist patterns become free-standing structures on a lower-cladding. This leads to uniform metal stripes with good reproducibility and effectively removes parasitic structures on the edge of the metal stripe in the image reversal photolithography process. By applying the newly developed process to polymer-based gold stripe waveguide fabrication, we improved the propagation losses about two times compared with that incurred by the conventional image-reversal process.

• ETRI Journal
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• v.35 no.2
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.