• 한국전기전자재료학회논문지
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• 제29권12호
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• pp.759-763
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• 2016

We demonstrate the utilization of ion gel gate dielectrics for operating non-volatile transistor memory devices based on polymer semiconductor thin films. The gating process in typical electrolyte-gated polymer transistors occurs upon the penetration and escape of ionic components into the active channel layer, which dopes and dedopes the polymer film, respectively. Therefore, by controlling doping and dedoping processes, electrical current signals through the polymer film can be memorized and erased over a period of time, which constitutes the transistor-type memory devices. It was found that increasing the thickness of polymer films can enhance the memory performance of device including (i) the current signal ratio between its memorized state and erased state and (ii) the retention time of the signal.

• 반도체디스플레이기술학회지
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• 제21권3호
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.46-50
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• 2008

The effect of physicochemical properties of solvents on the microstructure of polyvinyl carbazole (PVK) film for non-volatile polymer memory was investigated. For the solubilization of PVK molecules and the preparation of PVK films, four solvents with different physicochemical properties of the Hildebrand solubility parameter and vapor pressure were considered: chloroform, tetrahydrofuran (THF), 1,1,2,2-tetrachloroethane (TCE), and N,N-dimehtylformamide (DMF). The solubility of PVK molecules in the solvents was observed by ultravioletvisible spectroscopy. PVK molecules were observed to be more soluble in chloroform, with a low Hildebrand solubility parameter, than solvents with higher values. The aggregated size and micro-/nano-topographical properties of PVK films were characterized using optical and atomic force microscopes. The PVK film cast from chloroform exhibited enhanced surface roughness compared to that from TCE and DMF. It was also confirmed that the microstructure of PVK film has an effect on the performance of non-volatile polymer memory.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제23권7호
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• pp.428-433
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• 2017

최근 데이터센터, 소셜 네트워크 서비스 등과 같은 고성능 컴퓨팅을 요구하는 환경에서는 기존 하드디스크를 대체할 수 있는 고성능 비휘발성 메모리 저장장치의 수요가 급증하고 있다. 이러한 비휘발성 메모리의 성능은 호스트와 저장장치를 연결해주는 인터페이스에 따라 크게 좌우될 수 있다. 저장장치의 인터페이스는 계속 발전해왔으며, 기존 하드디스크에 기반을 둔 SAS/SATA 인터페이스를 대체할 수 있는 NVMe 인터페이스가 최근에 등장하였다. NVMe 인터페이스는 높은 확장성을 가지며 기존 인터페이스에 비해 낮은 지연시간을 제공한다. 본 논문은 다양한 워크로드를 통해 NVMe 저장장치의 성능을 평가하고 분석한다. 또한 NVMe 저장장치와 기존 SATA 저장장치와의 가격 대비 성능비를 비교하고 평가한다.

• 한국콘텐츠학회논문지
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• 제21권7호
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• pp.157-163
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• 2021

파일 시스템에서 하나의 쓰기 연산은 여러 데이터를 수정할 수 있지만, 이러한 파일 시스템의 변경들은 원자적으로 디스크에 써지지 않는다. 따라서 파일 시스템의 일관성을 위해 기존의 저널링 기법은 시스템 성능을 저하시키는 대신 충돌 일관성을 보장한다. 비휘발성 메모리를 저널 공간으로 사용하면 비휘발성 메모리의 낮은 지연 시간과 바이트 수준 접근성으로 성능 저하를 완화시킬 수 있다고 알려졌다. 그러나 비휘발성 메모리를 고려한 저널링 기법 중에서 확장성을 제공하는 것은 없다. 본 논문에서는 확장적 저널링을 위해 비휘발성 메모리상의 저널 공간을 여러 영역으로 분할하여 한 영역에 집중된 연산을 분산시킨다. 또한, 저널 영역별로 입출력 쓰레드를 두어 저장 장치에 데이터 쓰기 연산을 가속화한다. 제안된 기법을 JFS에 적용하여 고성능 저장장치를 탑재한 멀티코어 서버에서 이를 평가한다. 평가 결과는 제안된 기법이 기존의 NVM 기반 저널링 파일 시스템의 기법보다 성능이 우수함을 보여준다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권4호
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• 한국인터넷방송통신학회논문지
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• 제21권6호
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• pp.65-70
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• 2021

최근 모바일 앱의 수가 급증하면서 스마트폰의 메모리 크기 또한 크게 증가하고 있다. 메모리 매체인 DRAM은 모든 셀이 지속적인 전원재공급 연산을 수행해야 내용이 유지되는 휘발성 매체로 메모리 크기 증가 시 전력 소모도 그에 비례해 늘어난다. 최근 스마트폰의 메모리로 DRAM이 아닌 저전력의 비휘발성 메모리를 사용하여 배터리 소모를 줄이고자 하는 시도가 늘고 있다. 그러나, 비휘발성 메모리는 쓰기 연산에 취약성을 가지고 있어 이를 해결하기 위한 분석이 필요하다. 본 논문은 모바일 앱의 메모리 쓰기 참조 트레이스를 추출하고 그 특성을 다양한 각도에서 분석하였다. 본 논문의 연구 결과는 비휘발성 메모리가 메인 메모리로 채택되는 미래의 스마트폰 시스템에서 쓰기 효율성을 가진 메모리 관리 기법 설계에 널리 활용될 수 있을 것으로 기대된다.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.32-39
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• 2008

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single $SiO_2$ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.