• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.9-14
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• 2009

In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.5
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• pp.268-273
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• 2016

In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The $WO_x$ material was used between metal electrodes as the oxide insulator. The structure of the $Al/WO_x/TiN$ shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at -2.6V. The reset process from LRS to HRS occurred at 2.78V. The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable $V_{set}$ and $V_{reset}$ were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm's Law ${\rightarrow}$ Trap-Controlled Space Charge Limited Current ${\rightarrow}$ Ohm's Law) process in the positive voltage region.

• Journal of the Korean Ceramic Society
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• v.32 no.12
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• pp.1408-1416
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• 1995

Microstructure and ferroelectric properties of sol-gel derived PZT(52/48) and PT interlayered PZT(52/48) thin films on Pt/Ti/SiO2/Si substrates were investigated. Films were fabricated using Acetylacetone chelated PT and PZT(52/48) sols. PZT(52/48) thin films annealed at $700^{\circ}C$ for 20 min showed the rosette structure with the size of 1.2~1.6${\mu}{\textrm}{m}$ and the pyrochlore phse was contained. PT interlayered PZT thin films, which is inserted by PbTiO3 thin layer with the thickness of 130 $\AA$ between PZT thin film and electrode, consisted of a single perovskite phase after annealing above 55$0^{\circ}C$. They exhibited the uniform and columnar grains of 0.1~0.16${\mu}{\textrm}{m}$, which are applicable for microelectronic device including non-volatile memory. Typical P-E hysteresis loops could be obtained from PT interlayered PZT thin film at as low as the annealing temperature of 50$0^{\circ}C$. Ferroelectric properties of PT interlayered PZT thin films were improved as increasing annealing temperature up to $700^{\circ}C$, and then deteriorated at 75$0^{\circ}C$. PZT(52/48) and PT interlayered PZT(52/48) thin film annealed at $700^{\circ}C$ for 20 min displayed Ps=38.8$\mu$C/$\textrm{cm}^2$, Pr=10.0$\mu$C/$\textrm{cm}^2$, Ec=65.3 kV/cm and Ps=28.5$\mu$C/$\textrm{cm}^2$, Pr=9.8$\mu$C/$\textrm{cm}^2$, Ec=76.1 kV/cm, respectively.

• Journal of KIISE
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• v.42 no.12
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• pp.1480-1485
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• 2015

As SSDs are increasingly being used as high-performance storage or caches, attention is increasingly paid to the provision of SSDs with Quality-of-Service for I/O request streams of various applications in server systems. Since most SSDs are using the AHCI controller interface on a SATA bus, it is not possible to provide a differentiated service by distinguishing each I/O stream from others within the SSD. However, since a new SSD interface, the NVME controller interface on a PCI Express bus, has been proposed, it is now possible to recognize each I/O stream and schedule I/O requests within the SSD for differentiated services. This paper proposes Flash Operation Group Scheduling within NVME-based flash storage devices, and demonstrates through QEMU-based simulation that we can achieve a proportional bandwidth share for each I/O stream.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.181-186
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• 2015

With the rapid growth of semiconductor technologies, small-sized devices with powerful computing abilities are becoming a reality. As this environment has a limit on power supply, NVM storage that has a high density and low power consumption is preferred to HDD or SSD. However, legacy software layers optimized for HDDs should be revisited. Specifically, as storage performance approaches DRAM performance, existing I/O mechanisms and software configurations should be reassessed. This paper explores the challenges and implications of using NVM storage with a broad range of experiments. We measure the performance of a system with NVM storage emulated by DRAM with proper timing parameters and compare it with that of HDD storage environments under various configurations. Our experimental results show that even with storage as fast as DRAM, the performance gain is not large for read operations as current I/O mechanisms do a good job hiding the slow performance of HDD. To assess the potential benefit of fast storage media, we change various I/O configurations and perform experiments to quantify the effects of existing I/O mechanisms such as buffer caching, read-ahead, synchronous I/O, direct I/O, block I/O, and byte-addressable I/O on systems with NVM storage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Journal of KIISE
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• v.43 no.1
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• pp.27-33
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• 2016

Virtualization has become one of the most helpful techniques in computing systems, and today it is prevalent in several computing environments including desktops, data-centers, and enterprises. However, since I/O layers are implemented to be oblivious to the I/O behaviors on virtual machines (VM), there still exists an I/O scalability issue in virtualized systems. In particular, when a multi-queue solid state drive (SSD) is used as a secondary storage, each system reveals a semantic gap that degrades the overall performance of the VM. This is due to two key problems, accelerated lock contentions and the I/O parallelism issue. In this paper, we propose a novel approach, including the design of virtual CPU (vCPU)-dedicated queues and I/O threads, which efficiently distributes the lock contentions and addresses the parallelism issue of Virtio-blk-data-plane in virtualized environments. Our approach is based on the above principle, which allocates a dedicated queue and an I/O thread for each vCPU to reduce the semantic gap. Our experimental results with various I/O traces clearly show that our design improves the I/O operations per second (IOPS) in virtualized environments by up to 155% over existing QEMU-based systems.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.25-29
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• 2020

This study demonstrates direct-patternable amorphous TiO_x resistive switching (RS) device and the fabrication method using photochemical metal-organic deposition (PMOD). For making photosensitive stock solutions, Ti(IV) 2-ethylhexanoate was used as starting precursor. Photochemical reaction by UV exposure was observed and analyzed by Fourier transform infrared spectroscopy and the reaction was completed within 10 minutes. Uniformly formed 20 nm thick amorphous TiO_x film was confirmed by atomic force microscopy. Amorphous TiO_x RS device, formed as 6 × 6 ㎛ square on 4 ㎛ width electrode, showed forming-less RS behavior in ±4 V and on/off ratio ≈ 20 at 0.1 V. This result shows PMOD process could be applied for low temperature processed ReRAM device and/or low cost, flexible memory device.

• Journal of the Korean Ceramic Society
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• v.34 no.2
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• pp.202-208
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• 1997

Bi-layered SrBi2Ta2O9(SBT) films were deposited on Pt/Ti/SiO2/Si sibstrates by rf magnetron sputt-ering at room temperature and then were annealed at 75$0^{\circ}C$, 80$0^{\circ}C$ and 85$0^{\circ}C$ for 1 hour in oxygen at-mosphere. The film composition of SrBi2Ta2O9 was obtained after depositing at room temperature and annealing at 80$0^{\circ}C$. Excess 20mole% Bi2O3 and 30 mole% SrCO3 were added to the target to compensate for the lack of Bi and Sr in SBT film. 200 nm thick SBT film exhibited and dense microstructure, adielectric constant of 210, and a dissipation factor of 0.05 at 1 MHz frequency. The films exhibited Curie temperature of 32$0^{\circ}C$ and a dielectric constant of 314 at that temperature under 100 kHz frequency. The remanent polarization(2Pr) and the coercive field(2Ec) of the SBT films were 9.1 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm at an applied voltage of 3V, resspectively and the SBT film showed a fatigue-free characteristics up to 1010 cy-cles under 5V bipolar pulse. The leakage current density of the SBT film was about 7$\times$10-7A/$\textrm{cm}^2$ at 150 kV/cm. Fatigue-free SBT films prepared by rf magnetron sputtering can be suitable for application to non-volatile memory device.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.312-320
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• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.