• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.130-130
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• 2008

• Journal of Advanced Marine Engineering and Technology
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• v.31 no.4
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• pp.410-416
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• 2007

PRAM (Phase change random access memory) is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to change the heater electrode material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of heater electrode material parameters using finite element analysis. From the simulation. the reset current of PRAM cell is reduced from 2.0 mA to 0.72 mA as the electrical conductivity of heater is decreased from $1.0{\times}10^6\;(1/{\Omega}{\cdot}m$) to $1.0{\times}10^4\;(1/{\Omega}{\cdot}m$). As the thermal conductivity of heater is decreased, the reset current is slightly reduced. But the reset current of PRAM cell is not changed as the specific heat of heater is changed.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1335-1336
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• 2007

Among the emerging non-volatile memory technologies, phase change memories are the most attractive in terms of both performance and scalability perspectives. Phase-change random access memory(PRAM), compare with flash memory technologies, has advantages of high density, low cost, low consumption energy and fast response speed. However, PRAM device has disadvantages of set operation speed and reset operation power consumption. In this paper, we investigated scalability of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material to improve its properties. As a result, reduction of phase change region have improved electrical properties of PRAM device.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.139-144
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• 2019

For recent decades, Non-volatile Memory (NVM) technologies have been drawing a high attention both in industry and academia due to its high density and short latency comparable to that of DRAM. However, NVM devices has write endurance problem and thus the current data structures that have been built around DRAM-specific features including unlimited program cycles is inadequate for NVM, reducing the device lifetime significantly. In this paper, we revisit a red-black tree extensively adopted for data indexing across a wide range of applications, and make it to better fit for NVM. Specifically, we observe that the conventional red-black tree wears out the specific location of memory because of its rebalancing operation to ensure fast access time over a whole dataset. However, this rebalancing operation frequently updates the long-lived nodes, which leads to the skewed wear out across the NVM cells. To resolve this problem, we present a new swapping wear-leveling red-black tree that periodically moves data in the worn-out node into the young node. The performance study with real-world traces demonstrates the proposed red-black tree reduces the standard deviation of the write count across nodes by up to 12.5%.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Smart Media Journal
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• v.8 no.1
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• pp.19-26
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• 2019

At the opening ceremony of 2018 Winter Olympics in PyeongChang, an unknown cyber-attack occurred. The malicious code used in the attack is based on in-memory malware, which differs from other malicious code in its concealed location and is spreading rapidly to be found in more than 140 banks, telecommunications and government agencies. In-memory malware accounts for more than 15% of all malicious codes, and it does not store its own information in a non-volatile storage device such as a disk but resides in a RAM, a volatile storage device and penetrates into well-known processes (explorer.exe, iexplore.exe, javaw.exe). Such characteristics make it difficult to analyze it. The most recently released in-memory malicious code bypasses the endpoint protection and detection tools and hides from the user recognition. In this paper, we propose a method to efficiently extract the payload by unpacking injection through IDA Pro debugger for Dorkbot and Erger, which are in-memory malicious codes.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• Journal of Magnetics
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• v.7 no.3
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]