• 한국진공학회:학술대회논문집
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• 한국진공학회 2008년도 제35회 하계학술대회 초록집
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• pp.130-130
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• 2008

• Journal of Advanced Marine Engineering and Technology
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• 제31권4호
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• pp.410-416
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• 2007

PRAM (Phase change random access memory) is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to change the heater electrode material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of heater electrode material parameters using finite element analysis. From the simulation. the reset current of PRAM cell is reduced from 2.0 mA to 0.72 mA as the electrical conductivity of heater is decreased from $1.0{\times}10^6\;(1/{\Omega}{\cdot}m$) to $1.0{\times}10^4\;(1/{\Omega}{\cdot}m$). As the thermal conductivity of heater is decreased, the reset current is slightly reduced. But the reset current of PRAM cell is not changed as the specific heat of heater is changed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1335-1336
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• 2007

Among the emerging non-volatile memory technologies, phase change memories are the most attractive in terms of both performance and scalability perspectives. Phase-change random access memory(PRAM), compare with flash memory technologies, has advantages of high density, low cost, low consumption energy and fast response speed. However, PRAM device has disadvantages of set operation speed and reset operation power consumption. In this paper, we investigated scalability of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material to improve its properties. As a result, reduction of phase change region have improved electrical properties of PRAM device.

• 한국인터넷방송통신학회논문지
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• 제19권6호
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• pp.139-144
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• 2019

비휘발성 메모리는 높은 용량과 DRAM에 준하는 수준의 접근 성능을 제공하여 차세대 메모리 기술로 각광을 받고 있다. 최근 미국 반도체 시장을 중심으로 비휘발성 메모리가 상용화 되면서 그 활용 방법에 대한 관심은 더욱 고조되고 있다. 그러나 비휘발성 메모리는 쓰기 연산 시 셀이 마모되는 물리적 특성을 가지고 있어 마모 평준화를 수행하지 않으면 특정 셀의 과도한 마모로 메모리의 용량이 감소되는 현상이 발생할 수 있다. 본 논문은 현재 균형 이진 탐색 트리로 널리 사용되고 있는 레드-블랙 트리(Red-black tree)가 비휘발성 메모리 위에서 동작할 때 잦은 리밸런싱 동작이 트리의 상위 레벨 노드들의 빈번한 쓰기를 발생시켜 특정 셀의 마모를 가속화 시킨다는 것을 관찰하고, 이를 해결하기 위한 새로운 형태의 레드-블랙 트리를 제안한다. 실제 시스템에서 추출한 레드-블랙 트리 접근 트레이스를 활용한 성능평가에서 제안된 레드-블랙 트리는 기존 자료구조 대비 셀 간의 쓰기 횟수 편차를 최대 12.5% 감소시킴을 보여주었다.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• 스마트미디어저널
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• 제8권1호
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• pp.19-26
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• 2019

2018년 평창 동계 올림픽 개막식에서 출처를 알 수 없는 사이버공격이 발생하였다. 해당 공격에서 사용된 악성코드는 인 메모리 악성코드로 기존 악성코드와 은닉하는 장소가 다르며, 140개 이상의 은행, 통신, 정부 기관에서 발견될 정도로 빠르게 확산되고 있다. 인 메모리 악성코드는 전체 악성코드의 15%이상을 차지하며 매우 심각한 피해를 주고 있다. 비휘발성 저장장치로 알려진 하드디스크에 자신의 정보를 저장하는 것이 아닌 휘발성 저장장치 인 램의 특정 메모리영역인 프로세스에 삽입하여 악성행위를 일으키는 악성코드를 인 메모리 악성코드라고 지칭한다. 결과적으로 자신의 정보를 남기지 않아 메모리 탐지 도구를 우회하여 악성코드 분석가들의 분석을 어렵게 한다. 또한 현대 메모리는 갈수록 크기가 증가해 메모리 탐지 도구를 사용하여 메모리전체를 보기 힘들다. 따라서 본 논문에서는 인 메모리 악성코드인 Dorkbot과 Erger를 대상으로 IDA Pro 디버거를 통해 인젝션을 언 패킹하여 효율적으로 페이로드를 산출하는 방법을 제안한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.324-326
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• 2016

In this study, we have investigated indium tin zinc oxide (ITZO) as an active channel for non-volatile memory (NVM) devices. The electrical and memory characteristics of NVM devices using multi-stack gate insulator SiO2/SiOx/SiOxNy (OOxOy) with Si-rich SiOx for charge storage layer were also reported. The transmittance of ITZO films reached over 85%. Besides, ITZO-based NVM devices showed good electrical properties such as high field effect mobility of 25.8 cm2/V.s, low threshold voltage of 0.75 V, low subthreshold slope of 0.23 V/dec and high on-off current ratio of $1.25{\times}107$. The transmission Fourier Transform Infrared spectroscopy of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000-2300 cm-1. It indicates that many silicon phases and defect sources exist in the matrix of the SiOx films. In addition, the characteristics of NVM device showed a retention exceeding 97% of threshold voltage shift after 104 s and greater than 94% after 10 years with low operating voltage of +11 V at only 1 ms programming duration time. Therefore, the NVM fabricated by high transparent ITZO active layer and OOxOy memory stack has been applied for the flexible memory system.

• Journal of Magnetics
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• 제7권3호
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]