• Proceedings of the KIEE Conference
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• 2007.04b
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• pp.79-81
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• 2007

To detect partial discharge of 154kV joint box, we have made experiment by using the Al-foil electrode sensor. Generally the signals which are detected in partial discharge test of underground power transmission cable are accompanied with both noises of high voltage and noises of surrounding power cable. The most noise in near to end part of joint box is corona, beside other noises flowed from surrounding area. Partial discharge test is difficulty due to these noises. First, we had used Al-Foil sensor on middle joint box of 154[kV] underground transmission power cable, and then analyzed reliability of calibration signal by using the Al-Foil electrode sensor of NJB. From above results, decrement properties measured highly. But incase of injecting calibration signal of 500[pC] after measuring signals in IJB, the S/N ratio had about 25[dB] acquisition.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.2
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• pp.43-51
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• 2017

In this study, the effect of the steering vector model mismatch due to array uncertainties on the performance of array processing was analyzed through simulation, along with the alleviation of the model mismatch effect depending on array calibration. To increase the reliability of the simulation results, the actual steering vector of the array antenna obtained by electromagnetic simulation was used along with the Jahn's channel model, which is an experimental channel model. Based on the analysis of the power spectrum for each direction, beam pattern, and the signal-to-interference-plus-noise ratio of the beamformer output, the performance deterioration of array processing due to array uncertainties was examined, and the performance improvement of array processing through array calibration was also examined.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Proceedings of the KIEE Conference
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• 2007.04b
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• pp.75-78
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• 2007

To detect partial discharge of 154kV joint box, we have made experiment by using the HFCT sensor. Generally the signals which are detected in partial discharge test of underground power transmission cable are accompanied with both noises of high voltage and noises of surrounding power cable. The most noise in near to end part of joint box is corona, beside other noises flowed from surrounding area. Partial discharge test is difficulty due to these noises. First, we test reliability on both injection of calibration signal in NJB and removal of low frequency. After that, we had analyzed frequencies by measuring signals in IJB with 300[m] distance from NJB. Also we had measured S/N ratio by using the indirected injection method of calibration signal in IJB. In this experiment, two measurement methods were difference of detection acquisition, but these had the equal frequency properties.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2066-2068
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• 1999

In this paper, an optical fiber sensor(OF sensor) utilizing the principal of Sagnac interferometer was proposed to detect the discharge signals which generated from needle-sphere electrode system in insulating oil. The performance of OF sensor was checked by sinusoidal calibration signal generated by PZT acuator at 198kHz. The detected discharge signals consisted of acoustic signal and the electrical noise. The noise signal could be removed by digital low pass filter. It was demonstrated that the OF sensor in this research had a possibility to detect the discharge signals in power apparatus.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.11
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• pp.622-626
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• 2000

In this paper, an optical fiber sensor(OF sensor) utilizing the principal of Sagnac interferometer was proposed to detect the discharge signals. The needle-sphere electrode system in insulating oil generated the signals. The performance of OF sensor was checked by sinusoidal calibration signal generated by PZT actuator at 198KHz. The detected discharge signals consisted of acoustic signal and the electrical noise. The noise signal could be removed by digital low pass filter. It was demonstrated that the OF sensor in this research had a possibility to detect the discharge signals in power apparatus.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.476-477
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• 2007

This paper described the partial discharge (PD) measurement techniques for diagnosing gas-insulated switches in overhead power distribution system. A capacitive voltage probe to detect PD pulse was designed and fixed on the surface of a bushing. We also designed a coupling network to attenuate AC voltage by 270 dB, and a low-noise amplifier having the gain of 40 dB and 500 kHz~20 MHz 3 dB. From the calibration, it was calculated that the sensitivity of the measurement system was 0.94mV/pC. In the application experiment, we could measure a PD pulse of 45 pC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.135-144
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• 2003

This work proposes on-chip full CMOS current and voltage references for high-speed mixed-mode circuits. The proposed current reference circuit uses a digital-domain calibration method instead of a conventional analog calibration to obtain accurate current values. The proposed voltage reference employs internal reference voltage drivers to minimize the high-frequency noise from the output stages of high-speed mixed-mode circuits. The reference voltage drivers adopt low power op amps and small- sized on-chip capacitors for low power consumption and small chip area. The proposed references are designed, laid out, and fabricated in a 0.18 um n-well CMOS process and the active chip area is 250 um x 200 um. The measured results show the reference circuits have the power supply variation of 2.59 %/V and the temperature coefficient of 48 ppm/$^{\circ}C$ E.