• 한국전기전자재료학회논문지
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• 제23권7호
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• pp.575-579
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• 2010

The technologies of Ni/Cu plating contact is attributed to the reduced series resistance caused by a better contact conductivity of Ni with Si and the subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading was combined with the lower resistance of a metal silicide contact and an improved conductivity of the plated deposit. This improves the FF (fill factor) as the series resistance is reduced. This is very much requried in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A Selective emitter structure with highly dopeds regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing In this paper the formation of a selective emitter, and the nickel silicide seed layer at the front side metallization of silicon cells is considered. After generating the nickel seed layer the contacts were thickened by Cu LIP (light induced plating) and by the formation of a plated Ni/Cu two step metallization on front contacts. In fabricating a Ni/Cu plating metallization cell with a selective emitter structure it has been shown that the cell efficiency can be increased by at least 0.2%.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.260-260
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• 2009

In high-efficiency crystalline silicon solar cell, If high-efficiency solar cells are to be commercialized, It is need to develop superior contact formation method and material that can be inexpensive and simple without degradation of the solar cells ability. For reason of plated metallic contact is not only high metallic purity but also inexpensive manufacture. It is available to apply mass production. Especially, Nickel, Copper are applied widely in various electronic manufactures as easily formation is available by plating. Ni is shown to be a suitable barrier to Cu diffusin as well as desirable contact metal to silicon. Nickel monosilicide has been suggested as a suitable silicide due to its lower resistivitym lower sintering temperature and lower layer stress than $TiSi_2$. In this paper, Nickel as a seed layer and diffusion barrier is plated by electroless plating to make nickel monosilicide.

• 대한금속재료학회지
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• 제49권11호
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• pp.905-909
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surfaces. One of the available front metal contacts is Ni/Cu plating, which can be mass produced via asimple and inexpensive process. A selective emitter, meanwhile, involves two different doping levels, with higher doping (${\leq}30{\Omega}/sq$) underneath the grid to achieve good ohmic contact and low doping between the grid in order to minimize the heavy doping effect in the emitter. This study describes the formation of a selective emitter and a nickel silicide seed layer for the front metallization of silicon cells. The contacts were thickened by a plated Ni/Cu two-step metallization process on front contacts. The experimental results showed that the Ni layer via SEM (Scanning Electron Microscopy) and EDX (Energy dispersive X-ray spectroscopy) analyses. Finally, a plated Ni/Cu contact solar cell displayed efficiency of 18.10% on a $2{\times}2cm^2$, Cz wafer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1419-1421
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• 1995

Nickel micro-structures are fabricated by electroless plating which shows better uniformity. Positive resist AZ4562 of 7 um thickness is patterned with minimum width of 2 um on poly-silicon as for sacrificial layer. The growth rate of Ni electroless plating is 10um/h both for the seed layer of Pt and TiW. TiW is found to be more practical than Pt, since it is very difficult to remove Pt with negligible damage to Ni structures.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.429-429
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• 2010

TFT 제조 방법 중 LTPS (Low Temperature Polycrystalline Silicon)는 저온과 저비용 등의 이점으로 인하여 flat panel display 제작에 널리 사용된다. 이동도와 전류 점멸비 등에서 이점을 가지는 ELA(Excimer Laser Annealing)가 널리 사용되고 있지만, 이 방법은 uniformity 등의 문제점을 가지고 있다. 이를 극복하기 위한 방법으로 MICC(Metal Induced Capping Crystallization)이 사용되고 있다. 이 방법은 $SiN_x$, $SiO_2$, SiON등의 capping layer를 diffusion barrier로 위치시키고, Ni 등의 금속을 capping layer에 도핑 한 뒤, 다시 한번 열처리를 통하여 a-Si에 Ni을 확산시키킨다. a-Si 층에 도달한 Ni들이 seed로 작용하여 Grain size가 매우 큰 film을 제작할 수 있다. 채널의 grain size가 클 경우 grain boundary에 의한 캐리어 scattering을 줄일 수 있기 때문에 MIC 방법을 사용하였음에도 ELA에 버금가는 소자의 성능과 안정성을 얻을 수있었다. 본 연구에서는 large grain TFT의 Gate bias stress에 따른 소자의 안정성 측정 및 분석에 목표를 두었다.

• 센서학회지
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• 제17권3호
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• pp.183-187
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• 2008

A sub-ppm level MEMS gas sensor that can be used for the detection of formaldehyde (HCHO) is presented. It is realized by using a zinc oxide (ZnO) thin-film material with a Ni-seed layer as a sensing material and by bulk micromachining technology. To enhance sensitivity of the MEMS gas sensor with Ni-seed layer was embedded with ZnO sensing material and sensing electrodes. As experimental results, the changed sensor resistance ratio for HCHO gas was 9.65 % for 10 ppb, 18.06 % for 100 ppb, and 35.7 % for 1 ppm, respectively. In addition, the minimum detection level of the fabricated MEMS gas sensor was 10 ppb for the HCHO gas. And the measured output voltage was about 0.94 V for 10 ppb HCHO gas concentration. The noise level of the fabricated MEMS gas sensor was about 50 mV. The response and recovery times were 3 and 5 min, respectively. The consumption power of the Pt micro-heater under sensor testing was 184 mW and its operating temperature was $400^{\circ}C$.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.221-221
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• 2003

본 연구에서는 스핀밸브 다층박막에서 교환 바이어스에 영향을 끼치는 요인 중 하나인 강자성층과 반강자성층사이의 접합 계면에서의 표면 거칠기 [1,2]를 줄이기 위해 현재 반도체 공정에 사용되고 있는 이온빔 에칭 장비를 사용하여 스핀 밸브 다층박막의 씨앗층 에칭에 따른 교환 바이어스를 알아보고자 하였다. 스핀밸브 구조는 강자성층/비자성층/강자성층의 기본구조를 갖는데 이중 하나의 강자성층의 스핀방향이 반강자성층에 의해 고정되는 구조[3]로써 이러한 고정 효과를 교환 바이어스(exchange bias)라 부른다. 교환 바이어스(exchange bias)현상은 강자성과 반강자성의 접합계면에서 강한 상호 교환결합력에 의해 나타나는 현상으로 이러한 교환 바이어스 특성은 하드드라이브의 고밀도 자기헤드소자 및 비휘발성 자기 메모리소자에 응용되어 기존의 자기저항 소자의 특성을 크게 향상시킬 수 있게 되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2380-2382
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• 2005

UV-LIGA 공정을 이용하여 3차원 마이크로 인덕터 제작 기술에 관하여 연구하였다. 마이크로 인덕터의 코일, 비아(via), 코어(core)의 Multi-layer 제작을 위해 UV-LIGA 공정을 이용하였으며, 전해도금(electro plating)을 위한 씨올기(seed layer)로서는 e-beam evaporator를 이용하여 금속을 증착하였다. 3차원 마이크로 인덕터의 도금 방법으로는 전해도금을 사용하였으며, 코일과 비아 부분은 구리(Cu) 전해도금, 코어 부분은 니켈(Ni)과 철(Fe)의 합금인 퍼멀로이(Ni/Fe) 전해도금을 하였다. 3차원 마이크로 인덕터의 샘플크기로는 코어의 폭은 $300{\mu}m$, 전체 길이는 9.2mm, 두께는 $20{\mu}m$의 구조로 제작되었으며, 코일 부분은 폭이 $40{\mu}m$, 두께는 $30{\mu}m$이며, 코일턴 수는 70회의 구조로 제작하였다.

• 한국초전도ㆍ저온공학회논문지
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• 제9권3호
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• pp.5-8
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• 2007

All three buffer layers of $Y_2O_3$, YSZ, and $CeO_2$ have been deposited on the biaxially textured metal substrates using rf-sputtering method, The first 50-70nm thick $Y_2O_3$ films were grown epitaxially on biaxially textured metal substrates as a seed layer and followed by the diffusion barrier ${\sim}100nm$ thick YSZ and subsequent capping layer ${\sim}200nm$ thick $CeO_2$ deposited epitaxially on top of $Y_2O_3$ seed layer. The epitaxial orientation of all three layers were all (100) grown with rocking curve Full Width at Half Maximum(FWHM) of $4-5^{\circ}$ and in plane phi-scan FWHM of $6-8^{\circ}$ using X -ray diffraction analysis. The NiO phases formed during the $Y_2O_3$ seed layer deposition seem to degrade the crystallinity and roughen the surface morphology of the following layer observed by AFM(Atomic Force Microscopy). The buffered tapes were used as substrates for long length YBCO coated conductors with high critical current density $J_c$. The five multi-turn of metal tapes was employed to increase the thickness of films and production rate to compensate the low growth rate of rf-sputtering method.