• 전력전자학회논문지
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• 제22권4호
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• pp.369-372
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• 2017

This paper presents a control scheme for three-level NPC inverters using small DC-link capacitors. To reduce the inverter system volume, the film capacitor with small capacitance is a promising candidate for the DC-link. When small capacitors are applied in a three level inverter, however, the AC ripple component increases in the DC-link NPV (neutral point voltage). In addition, the three-phase input grid currents are distorted when the DC-link capacitors are fed by diode rectifier. In this paper, the additional circuit is applied to compensate for small capacitor systems defect, and the offset voltage injection method is presented for the stabilization in NPV. These two proposed processes evidently ensure the quality improvement of the input grid currents and output load currents. The feasibility of the proposed method is verified by experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.42-45
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• 1997

A synchronous solid-state var compensator(SSVC) system which employs a three-phase neutral-point-darned (NPC) inverter is presented and analyzed for high voltage and high power applications. The proposed SSVC system can compensate for leading and lagging displacement factor. An optimal pulse-width-modulation (PWM) is used as a means of reducing the size of reactive components. A equivalent model is obtained using DQ-transform, and the characteristic of open-loop system are archived from DC and AC analyzes. A $\alpha$ phase-shift control is suggested using a self-controlled dc bus.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.63-69
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• 1998

A new current controlled PWM technique with NPC structure is proposed in this paper. A current controlled PWM technique with neutral-point-clamped pulse-width modulation inverter composed of main switching devices which operates as switch for PWM and auxiliary switching devices to clamp the output terminal potential to the neutral point potential is described. The proposed current controller has a first and second current band. The switching pattern will be made by the first current band. According to the second current band, the output state of the switching pattern is changed into positive and negative state. This inverter output contains less harmonic content and lower switching frequency than that of conventional current controlled PWM technique at the same current limit. Two inverters are compared analytically and the performance is investigated by the computer simulation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.316-317
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• 2018

This paper propse the DC link capacitor voltage balancing control for three level neutral point clamped converter with harmonic component injection method. The injcetion voltage consists of harmonic component and DC link capacitor voltage difference. Theoretical analysis is provided to balance the DC link voltage, and it shows that harmonic component compensates the unbalanced condition between the capacitors. Both simulations and experiments are carried out to show that the voltage unbalance have been decreased by the proposed method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.315-316
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• 2015

본 논문에서는 3-레벨 Neutral-Point-Clamped (NPC) 인버터의 DC-Link 중성점 전압 리플을 저감하여 인버터 출력 전압의 품질 신뢰성 향상이 가능한 새로운 Discontinuous Pulse Width Modulation (DPWM) 기법을 제안한다. NPC 인버터에서는 두 개의 커패시터로 이루어진 DC-Link 구조로 인해 상, 하단 DC-Link 커패시터 전압 불평형인 상황에서 DC-Link 중 성점 전압 리플이 발생한다. 중성점 전압 리플 발생 시 출력 전압의 품질을 보장할 수 없으며, 민감한 부하에 손상을 입힐 수 있다. 제안한 DPWM 알고리즘은 DC-Link 커패시터 전압을 조정하는 두 개의 오프셋을 사용하여 중성점 전압 리플을 저감한다. 또한, 시뮬레이션을 통해 본 논문에서 제안한 알고리즘의 타당성을 검증한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.315-316
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• 2012

Three-level neutral point clamping (NPC) converter has been widely applied in high power drive system. And in this paper, a novel method is proposed to realize this algorithm based on FPGA, And the system is consist of two parts, the DSP part and FPGA part, the DSP part includes the control algorithms and the FPGA part works to generate and putout 12 PWM pulses. And the system is tested and verified using both simulation and experimentation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.324-325
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• 2019

본 논문에서는 3-Level Neutral-Point-Clamped (NPC) 인버터의 중성점 리플 전압 예측 기법을 제안한다. 산업용 계통 연계형 인버터의 경우, 계통 규정을 만족하기 위하여 전압 강하와 같은 계통 사고 발생 시 계통에 협조할 수 있도록 무효전류 보상이 요구된다. NPC 인버터는 두 개의 커패시터가 직렬로 이루어진 구조로 무효전류 출력 시 상단과 하단의 커패시터 전압에 3차 중성점 리플 전류로 인해 중성점 리플 전압이 발생한다. 따라서 중성점 리플 전압을 고려하여 출력 전류에 보상하지 않으면 무효전류의 품질에 악영향을 끼칠 수 있다. 본 논문에서는 하나의 DC 전압센서를 통하여 중성점 전류를 예측하고, 중성점 리플 전압을 보상하는 알고리즘을 제안한다. Hardware In the Loop (HIL) Simulation을 통하여 본 논문에서 제안한 알고리즘의 타당성을 검증한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.485-486
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• 2016

This paper proposes a new hybrid five-level voltage-source inverter topology, based on the conventional five-level active neutral-point-clamped topology (5L-ANPC), where the lower number of switching devices is required, resulting in saving the cost. The operating principle and control method of the proposed topology is described. The comparison of THD, power losses, loss distribution, and cost of components are evaluated among the proposed topology, the 5L-ANPC and 5L-DCI (diode-clamped inverters) topology.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.487-488
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• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.3-4
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• 2011

This paper presents a survey of floating power supply based on bootstrap operation for three-level voltage-source inverters. The floating power supply for upper switches is achieved by the bootstrap capacitor charged during on-time of the switch underneath. Hence, a large number of bulky isolated DC/DC power supplies for each gate driver are reduced. The Pspice simulation results show the behavior of bootstrap devices and the performance of bootstrap capacitor voltage.