• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.339-345
• /
• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.8
• /
• pp.610-618
• /
• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.19 no.3
• /
• pp.165-171
• /
• 2019

The study of the computer architecture has shown that major improvements in price-to-energy performance stems from domain-specific hardware development. This paper analyzes the tensor processing unit (TPU) ASIC which can accelerate the reasoning of the artificial neural network (NN). The core device of the TPU is a MAC matrix multiplier capable of high-speed operation and software-managed on-chip memory. The execution model of the TPU can meet the reaction time requirements of the artificial neural network better than the existing CPU and the GPU execution models, with the small area and the low power consumption even though it has many MAC and large memory. Utilizing the TPU for the tensor flow benchmark framework, it can achieve higher performance and better power efficiency than the CPU or CPU. In this paper, we analyze TPU, simulate the Python modeled OpenTPU, and synthesize the matrix multiplication unit, which is the key hardware.

• International Journal of Computer Science & Network Security
• /
• v.23 no.10
• /
• pp.147-156
• /
• 2023

Electronic voting machines (EVMs) are replacing research ballots due to the errors involved in the manual counting process and the lengthy time required to count the votes. Even though these digital recording electronic systems are advancements, they are vulnerable to tampering and electoral fraud. The suspected vulnerabilities in EVMs are the possibility of tampering with the EVM's memory chip or replacing it with a fake one, their simplicity, which allows them to be tampered with without requiring much skill, and the possibility of double voting. The vote data is shared among all network devices, and peer-to-peer verification is performed to ensure the vote data's authenticity. To successfully tamper with the system, all of the data stored in the nodes must be changed. This improves the proposed system's efficiency and dependability. Elections and voting are fundamental components of a democratic system. Various attempts have been made to make modern elections more flexible by utilizing digital technologies. The fundamental characteristics of free and fair elections are intractability, immutability, transparency, and the privacy of the actors involved. This corresponds to a few of the many characteristics of blockchain-like decentralized ownership, such as chain immutability, anonymity, and distributed ledger. This working research attempts to conduct a comparative analysis of various blockchain technologies in development and propose a 'Blockchain-based Electronic Voting System' solution by weighing these technologies based on the need for the proposed solution. The primary goal of this research is to present a robust blockchain-based election mechanism that is not only reliable but also adaptable to current needs.

• Animal Bioscience
• /
• v.37 no.4
• /
• pp.622-630
• /
• 2024

Objective: Pig breeders cannot obtain phenotypic information at the time of selection for sow lifetime productivity (SLP). They would benefit from obtaining genetic information of candidate sows. Genomic data interpreted using deep learning (DL) techniques could contribute to the genetic improvement of SLP to maximize farm profitability because DL models capture nonlinear genetic effects such as dominance and epistasis more efficiently than conventional genomic prediction methods based on linear models. This study aimed to investigate the usefulness of DL for the genomic prediction of two SLP-related traits; lifetime number of litters (LNL) and lifetime pig production (LPP). Methods: Two bivariate DL models, convolutional neural network (CNN) and local convolutional neural network (LCNN), were compared with conventional bivariate linear models (i.e., genomic best linear unbiased prediction, Bayesian ridge regression, Bayes A, and Bayes B). Phenotype and pedigree data were collected from 40,011 sows that had husbandry records. Among these, 3,652 pigs were genotyped using the PorcineSNP60K BeadChip. Results: The best predictive correlation for LNL was obtained with CNN (0.28), followed by LCNN (0.26) and conventional linear models (approximately 0.21). For LPP, the best predictive correlation was also obtained with CNN (0.29), followed by LCNN (0.27) and conventional linear models (approximately 0.25). A similar trend was observed with the mean squared error of prediction for the SLP traits. Conclusion: This study provides an example of a CNN that can outperform against the linear model-based genomic prediction approaches when the nonlinear interaction components are important because LNL and LPP exhibited strong epistatic interaction components. Additionally, our results suggest that applying bivariate DL models could also contribute to the prediction accuracy by utilizing the genetic correlation between LNL and LPP.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.31-38
• /
• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.12
• /
• pp.210-216
• /
• 2014

In this paper, it was proposed to develop front and rear image monitoring system for vehicle that help a driver to cope with urgent situation about a dangerous element. When parking a vehicle, the risk factors to be formed by the dead zone can be resolved by using anterior and posterior cameras of the vehicle. In embedded system environment, a SoC(System on Chip) and two high-resolution CMOS (Complementary metal-oxide-semiconductor) image sensors were used to transfer two high-resolution image data through he TCP/ IP-based network. To transfer image data through he TCP/ IP-based network, the images received by two cameras were compressed by using H.264 and they were transmitted with wireless method(Wi-Fi) by using real-time transport protocol (Real-time Transport Protocol). Transmission loss, transmission delay and transmission limit were solved in wireless (Wi-Fi) environment and the bit-rate of two image data compressed by H.264 was adjusted. And the system for the optimal transmission in wireless (Wi-Fi) environment was materialized and experimented.

• Journal of Information Processing Systems
• /
• v.8 no.1
• /
• pp.159-174
• /
• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.239-240
• /
• 2012

With advancements in semiconductor device technologies, manufacturing processes are getting more complex and it became more difficult to maintain tighter process control. As the number of processing step increased for fabricating complex chip structure, potential fault inducing factors are prevail and their allowable margins are continuously reduced. Therefore, one of the key to success in semiconductor manufacturing is highly accurate and fast fault detection and classification at each stage to reduce any undesired variation and identify the cause of the fault. Sensors in the equipment are used to monitor the state of the process. The idea is that whenever there is a fault in the process, it appears as some variation in the output from any of the sensors monitoring the process. These sensors may refer to information about pressure, RF power or gas flow and etc. in the equipment. By relating the data from these sensors to the process condition, any abnormality in the process can be identified, but it still holds some degree of certainty. Our hypothesis in this research is to capture the features of equipment condition data from healthy process library. We can use the health data as a reference for upcoming processes and this is made possible by mathematically modeling of the acquired data. In this work we demonstrate the use of recurrent neural network (RNN) has been used. RNN is a dynamic neural network that makes the output as a function of previous inputs. In our case we have etch equipment tool set data, consisting of 22 parameters and 9 runs. This data was first synchronized using the Dynamic Time Warping (DTW) algorithm. The synchronized data from the sensors in the form of time series is then provided to RNN which trains and restructures itself according to the input and then predicts a value, one step ahead in time, which depends on the past values of data. Eight runs of process data were used to train the network, while in order to check the performance of the network, one run was used as a test input. Next, a mean squared error based probability generating function was used to assign probability of fault in each parameter by comparing the predicted and actual values of the data. In the future we will make use of the Bayesian Networks to classify the detected faults. Bayesian Networks use directed acyclic graphs that relate different parameters through their conditional dependencies in order to find inference among them. The relationships between parameters from the data will be used to generate the structure of Bayesian Network and then posterior probability of different faults will be calculated using inference algorithms.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.32 no.7
• /
• pp.83-90
• /
• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.