• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.689-694
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• 2014

An SPLC (Safety Programmable Logic Controller) must be designed to meet the highest safety standards, IEEE 1E, and should guarantee a level of fault-tolerance and high-reliability that ensures complete error-free operation. In order to satisfy these criteria, I/O modules, communication modules, processor modules and bus modules of the SPLC have been configured in triple or dual modular redundancy. The redundant modules receive the same data to determine the final data by the voting logic. Currently, the processor of each rx module performs the voting by deciding on the final data. It is the intent of this paper to prove the improvement on the current system, and develop a voting system for multiple data on a system bus level. The new system bus protocol is implemented based on a TCN-MVB that is a deterministic network consisting of a master-slave structure. The test result shows that the suggested system is better than the present system in view of its high utilization and improved performance of data exchange and voting.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.1-9
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• 1999

As our society turns into the information age from the industrial one, the ministry of information and communication has set up functional software standards for electronic approval systems Several software houses have developed such systems in the client/server environment and subsequently for the intranet. Although electronic approval systems for the intranet have the advantages of less costly implementation and ease of use, they create heavy network traffic, and have a poor document processing functionality resulting from the lack of document processor in web environments. This paper describes a system design that web browsers utilize the resources of clients by adopting the ActiveX technique in order to improve such mallets mentions above. In other words, to use the Hangul word processor as a document processor, the ActiveX control and the Hangul DDE API have been implemented in the form of the DDE server/client, which is capable of mutual communication, and the flow of electronic approve system has been controled by connecting. As a result of running the implemented system lot three months through a real company in multi-server environment, it shows the high usage of electronic approval system as the tate roaches 75%-93% for some departments.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1096-1101
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• 2004

By a tremendous expansion of Internet users, there's a number effects that cause the phenomenon of bottlenecked switching packets from routers. In order to tear down this problem, distributed system is applicable to almost every highly performed router systems. The main processor of distributed system, which manages routing table, commands IPC to delivering the forwarding table line processor that eases functionalities of the router. This makes the system having wired-speed forwarding function based on the hardware so that the performance of the network can be enhanced. Therefore, IPC, which assign a part of router, is necessary to exchange data smoothly and the constitution of IPC using Ethernet is widely adapted as a method for saving investment. In this paper, R-IPC mechanism improve the packet-processing rate over 10% through changed from defect of conventional Ethernet IPC, that is, 2 layer processing to TCP/IP or UDP/ IP into 1 layer processing for efficient packet forwarding.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.1
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• pp.13-19
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• 2011

In this paper, a visual surveillance system using SOPC based NIOS II embedded processor and C2H compiler was implemented. In this system, the IP is constructed by C2H compiler for the output of the camera images, image processing, serial communication and network communication, then, it is implemented to effectively control each IP based on the SOPC and the NIOS II embedded processor. And, an algorithm which updates the background images for high speed and robust detection of the moving objects is proposed using the Adaptive Gaussian Mixture Model(AGMM). In results, it can detecte the moving objects(pedestrians and vehicles) under day-time and night-time. It is confirmed that the proposed AGMM algorithm has better performance than the Adaptive Threshold Method(ATM) and the Gaussian Mixture Model(GMM) from our experiments.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.4 s.316
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• pp.1-9
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• 2007

An embedded system is implemented in this work by removing PCMCIA dedicate controller chip from ARM processor based embedded Linux system. In this paper, we propose PCMCIA interface architecture by using Ad hoc methods for wireless network. The proposed system is developed based on S3C2410A processor and it is interfaced with PCMCIA socket by using combinational digital logic circuits. It is interesting to observe that Ad hoc interface provides $97.9%{\sim}102.49%$ performance when compared with dedicate controller systems. The results indicate that the proposed method simplifies the system without loss of performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2340-2352
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• 1994

Under the current IN(Intelligent Network) Architecture, most of their function were performed in SSP(Service Switching point), so the provision or modification of service was limited. To over come these limitation, the structure of 'AIN(Advanced Intelligent Network)' emerged. In this paper, SSP for AIN structure is designed and its performance is evaluated. In other words, the requirements for AIN service implementation are specified on the basis of ITU-T Recommendations. From these requirments and TDX-10 Exchange architecture, the SSP for AIN structure is designed, and its performance is analyzed through the method of simulation and analytical modeling. As a conclusion of this paper, when the system is operated as a standard model, the maximum throughput is 1,270,000 BHCA for Free Phone Service and 1,190,000 BHCA for Credit Call Service. The processors in INS(Interconnection Network Subsystem) are proved to be bottleneck elements. To enhance the performance, several suggestions such as processor and link speedup, and other D_bus service policy are proposed.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.31-46
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• 1997

In this paper, a parallel Optimal Best-First search Branch-and-Bound(B&B) algorithm(pobs) is designed and evaluated for MIN-based multiprocessor systems. The proposed algorithm decomposes a problem into G subproblems, where each subproblem is processed on a group of P processors. Each processor group uses tile sub-Global Best-First search technique to find a local solution. The local solutions are broadcasted through the network to compute the global solution. This broadcast provides not only the comparison of G local solutions but also the load balancing among the processor groups. A performance analysis is then conducted to estimate the speed-up of the proposed parallel B&B algorithm. The analytical model is developed based on the probabilistic properties of the B&B algorithm. It considers both the computation time and communication overheads to evaluate the realistic performance of the algorithm under the parallel processing environment. In order to validate the proposed evaluation model, the simulation of the parallel B&B algorithm on a MIN-based system is carried out at the same time. The results from both analysis and simulation match closely. It is also shown that the proposed Optimal Best-First search B&B algorithm performs better than other reported schemes with its various advantageous features such as: less subproblem evaluations, prefer load balancing, and limited scope of remote communication.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.10-19
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• 1986

This is the last part of the four-part describing the development of a packet-switched computer communication network named the KORNET. In this paper we describe the design and implementation of the packet assembler/dissassembler (PAD) protocol for the asynchronous channel service, and of the network management softwares. The line processing module-B(LPMB) system supporting the asynchronous line includes a PAD protocol, a packet mode DTE/DCE protocol converting to the X.25 protocol, and the asynchronous receiver/transmitter(ART) software. The network management software is operated in master central processing module(MCPM) which includes virtual circuit management (VCM) managing the user channel, the routing management and the high level protocol for communication between the network management center (NMC) and the network node processor(NNP). In this paper, the design, implementation and operation of the softwares for the above service functions will be described in detail.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.05a
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• pp.1-5
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• 2002

The purpose of this paper is developing a speech recognition module in a wheelchair for the sake of convenience. of the disability. For this system, we used TMS320C32 as a main processor; eliminated noise by applying Winer filler while considering characteristics of noise environment in pre-processing stage, and; extracted 12 feature patterns per france using LPC&Cepstrum. Then, we implemented the hybrid form combining DTW (Dynamic Time Warping), which is generally used for isolated words in the conventional algorithms, in the recognition Part, and NN (Neural network) to prevent any error of recognition. In this research, we achieved a recognition rate of more than 96% on isolated words when DTW and Hybrid forms were individually experimented in noise environment