• 제목/요약/키워드: Negative gate bias temperature illumination

검색결과 3건 처리시간 0.016초

Correlation between spin density and Vth instability of IGZO thin-film transistors

  • Park, Jee Ho;Lee, Sohyung;Lee, Hee Sung;Kim, Sung Ki;Park, Kwon-Shik;Yoon, Soo-Young
    • Current Applied Physics
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    • 제18권11호
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    • pp.1447-1450
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    • 2018
  • The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

SiO2 완충층 두께에 따른 비정질 InGaZnO Pseudo-MOS Field Effect Transistor의 신뢰성 평가 (Effect of SiO2 Buffer Layer Thickness on the Device Reliability of the Amorphous InGaZnO Pseudo-MOS Field Effect Transistor)

  • 이세원;황영현;조원주
    • 한국전기전자재료학회논문지
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    • 제25권1호
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    • pp.24-28
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    • 2012
  • In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

Atomic Layer Deposited ZrxAl1-xOy Film as High κ Gate Insulator for High Performance ZnSnO Thin Film Transistor

  • Li, Jun;Zhou, You-Hang;Zhong, De-Yao;Huang, Chuan-Xin;Huang, Jian;Zhang, Jian-Hua
    • Electronic Materials Letters
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    • 제14권6호
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    • pp.669-677
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    • 2018
  • In this work, the high ${\kappa}$ $Zr_xAl_{1-x}O_y$ films with a different Zr concentration have been deposited by atomic layer deposition, and the effect of Zr concentrations on the structure, chemical composition, surface morphology and dielectric properties of $Zr_xAl_{1-x}O_y$ films is analyzed by Atomic force microscopy, X-ray diffraction, X-ray photoelectron spectroscopy and capacitance-frequency measurement. The effect of Zr concentrations of $Zr_xAl_{1-x}O_y$ gate insulator on the electrical property and stability under negative bias illumination stress (NBIS) or temperature stress (TS) of ZnSnO (ZTO) TFTs is firstly investigated. Under NBIS and TS, the much better stability of ZTO TFTs with $Zr_xAl_{1-x}O_y$ film as a gate insulator is due to the suppression of oxygen vacancy in ZTO channel layer and the decreased trap states originating from the Zr atom permeation at the $ZTO/Zr_xAl_{1-x}O_y$ interface. It provides a new strategy to fabricate the low consumption and high stability ZTO TFTs for application.