• Title/Summary/Keyword: Nano-scale Process

Search Result 253, Processing Time 0.028 seconds

Fabrication of Hydroxyapatite-coated Zirconia by Room Temperature Spray Process and Microstructural Change by Heat-treatment (상온 분사법에 의한 수산화아파타이트 코팅 지르코니아의 제조 및 미세구조에 미치는 열처리 효과)

  • Lee, Jong Kook;Eum, Sangcheol;Kim, Jaehong;Jang, Woo Yang
    • Journal of the Korean Society for Heat Treatment
    • /
    • v.28 no.1
    • /
    • pp.17-23
    • /
    • 2015
  • Hydroxyapatite coatings were fabricated by a room temperature spray method on zirconia substrates and the influence of heat-treatment on their microstructure was also investigated. Phase composition of coated hydroxyapatite films was similar to the starting powder, but the grain size of hydroxyapatite particles was reduced to the size of nano-scale about 100 nm. Grain size, particle compactness, and adhesiveness to zirconia of hydroxyapatite coatings were increased with heat-treatment temperature, but some of cracks by heat-treatment above $1100^{\circ}C$ were initiated between hydroxyapatite coatings and zirconia substrate. Heat-treated hydroxyapatite layers show the dissolution in SBF solution for 5 days. Hydroxyapatite-coated specimen heat-treated at $1100^{\circ}C$ for 1 h has a good biocompatibility, which specimen induced the nanocrystalline hydroxyapatite precipitates on the coating surface by the immersion in SBF solution for 5 days.

Multi-stage forming analysis of milli component for improvement of forming accuracy (밀리부품 성형 정밀도 향상을 위한 다단계 미세성형 해석)

  • Yoon, J.H.;Huh, H.;Kim, S.S.;Choi, T.H.;Na, G.H.
    • Proceedings of the Korean Society for Technology of Plasticity Conference
    • /
    • 2003.10a
    • /
    • pp.97-100
    • /
    • 2003
  • Globally, the various machine components, as in electronics and communications, are demanded to being high-performance and micro-scale with abrupt development of the fields of computers, mobile communications. As this current tendency, production of the parts that must have high accuracy, so called milli-structure, are accomplished by the method of top-down, differently as in the techniques of MEMS, NANO. But, in the case of milli-structure, production procedure is highly costs, difficult and demands more accurate dimension than the conservative forming, processing technique. In this paper, forming analysis of the micro-former as the milli-structure are performed and then calculate the punch force etc. This information calculated is applied to decide the forming capacity of micro-former and design the process of forming stage, dimension of dies in another forming bodies. And, for the better precise forming analysis, elasto-plastic analysis is to be performed, then the consideration about effect of elastic recovery when punch and die are unloaded, have to be discussed in change of dimensions.

  • PDF

Electrochemical studies of nano-scale solid electrolyte powder prepared by chemical synthesis process (화학적합성법에 의한 나노 고체 전해질 분말 합성 및 전기화학적 평가)

  • Kim, Young-Mi;Shin, Yu-Cheol;Kim, Ho-Sung
    • 한국신재생에너지학회:학술대회논문집
    • /
    • 2009.06a
    • /
    • pp.295-298
    • /
    • 2009
  • Oxygen ionic conductors of CeScSZ electrolyte in SOFC unit cell are applied to anode and cathode as well as electrolyte to have the triple-phase-boundaries of electrochemical reaction, and it is required to decrease the sintering temperature of anode-supported electrolyte by the nanoscale of CeScSZ electrolyte powder. In this report, nanoscale CeScSZ electrolyte powder was synthesized by chemical synthesis method. The particle size, surface area and morphology of the powder were observed by SEM and BET. Thin film electrolyte of under $10{\mu}m$ was fabricated by tape casting using the synthesized CeScSZ electrolyte powder, and ionic conductivity and gas permeability of electrolyte film were evaluated. Finally the SOFC unit cell was fabricated using the anode-supported electrolyte prepared by a tape casting method and co-sintering, in which the active layer, measuring $20{\mu}m$, was introduced in the anode layer to provide a more efficient reaction. Electrochemical evaluations of the SOFC unit cell, including measurements such as power density and impedance, were performed and analyzed.

  • PDF

Fabrication of SOI FinFET devices using Aresnic solid-phase-diffusion (비소 고상확산방법을 이용한 MOSFET SOI FinFET 소자 제작)

  • Cho, Won-Ju;Koo, Hyun-Mo;Lee, Woo-Hyun;Koo, Sang-Mo;Chung, Hong-Bay
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2006.11a
    • /
    • pp.133-134
    • /
    • 2006
  • A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

  • PDF

Synchrotron X-ray Reflectivity Studies on Nanoporous Low Dielectric Constant Organosilicate Thin Films

  • Oh, Weon-Tae;Park, Yeong-Do;Hwang, Yong-Taek;Ree, Moon-Hor
    • Bulletin of the Korean Chemical Society
    • /
    • v.28 no.12
    • /
    • pp.2481-2485
    • /
    • 2007
  • Spatially resolved, quantitative, non-destructive analysis using synchrotron x-ray reflectivity (XR) with subnano-scale resolution was successfully performed on the nanoporous organosilicate thin films for low dielectric applications. The structural information of porous thin films, which were prepared with polymethylsilsesquioxane and thermally labile 4-armed, star-shaped poly(ε-caprolactone) (PCL) composites, were characterized in terms of the laterally averaged electron density profile along with a film thickness as well as a total thickness. The thermal process used in this work caused to efficiently undergo sacrificial thermal degradation, generating closed nanopores in the film. The resultant nanoporous films became homogeneous, well-defined structure with a thin skin layer and low surface roughness. The average electron density of the calcined film reduced with increase of the initial porogen loading, and finally leaded to corresponding porosity ranged from 0 to 22.8% over the porogen loading range of 0-30 wt%. In addition to XR analysis, the surface and the inner structures of films are investigated and discussed with atomic force and scanning electron microscopy images.

Layer-by-layer assembled graphene oxide films and barrier properties of thermally reduced graphene oxide membranes

  • Kim, Seon-Guk;Park, Ok-Kyung;Lee, Joong Hee;Ku, Bon-Cheol
    • Carbon letters
    • /
    • v.14 no.4
    • /
    • pp.247-250
    • /
    • 2013
  • In this study, we present a facile method of fabricating graphene oxide (GO) films on the surface of polyimide (PI) via layer-by-layer (LBL) assembly of charged GO. The positively charged amino-phenyl functionalized GO (APGO) is alternatively complexed with the negatively charged GO through an electrostatic LBL assembly process. Furthermore, we investigated the water vapor transmission rate and oxygen transmission rate of the prepared (reduced GO $[rGO]/rAPGO)_{10}$ deposited PI film (rGO/rAPGO/PI) and pure PI film. The water vapor transmission rate of the GO and APGO-coated PI composite film was increased due to the intrinsically hydrophilic property of the charged composite films. However, the oxygen transmission rate was decreased from 220 to 78 $cm^3/m^2{\cdot}day{\cdot}atm$, due to the barrier effect of the graphene films on the PI surface. Since the proposed method allows for large-scale production of graphene films, it is considered to have potential for utilization in various applications.

Thermal Stability Improvement of Ni-Germanide Using Ni-N(1%) for Nano Scale Ge-MOSFET Technology (나노급 Ge-MOSFET를 위한 Ni-N(1%)을 이용한 Ni-germanide의 열 안정성 개선)

  • Yim, Kyeong-Yeon;Park, Kee-Young;Zhang, Ying-Ying;Li, Shi-Guang;Zhong, Zhun;Jung, Soon-Yen;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2008.11a
    • /
    • pp.17-18
    • /
    • 2008
  • In this paper, 1%-nitrogen doped Nickel was used for improvement of thermal stability of Ni-Germanide. Proposed Ni-N(1%)/TiN structure has shown better thermal stability, sheet resistance and less agglomeration characteristic than pure Ni/TiN structure. During the germanidation process, it is believed that the nitrogen atoms in the deposited nickel layer can suppress the agglomeration of Ni germanide by retarding the diffusion of Ni atoms toward silicon layer, hence improve the thermal stability of Ni-germanide.

  • PDF

Thermal Stability Improvement of Ni-germanide using Ni-Co alloy for Ge-MOSFETs Technology (Ge-MOSFETs을 위한 Ni-Co 합금을 이용한 Ni-germanide의 열안정성 개선)

  • Park, Kee-Young;Jung, Soon-Yen;Zhang, Ying-Ying;Han, In-Shik;Li, Shi-Guang;Zhong, Zhun;Shin, Hong-Sik;Kim, Yeong-Cheol;Kim, Jae-Jun;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.21 no.8
    • /
    • pp.733-737
    • /
    • 2008
  • In this paper, Ni-Co alloy was used to improve thermal stability of Ni Germanide. It was found that uniform germanide is obtained on epitaxial Ge-on-Si substrate by employing Ni-Co alloy. Moreover, neither agglomeration nor penetration is observed during post-germanidation annealing process. The thermal stability of Ni germanide using Ni-Co alloy is improved due to the less agglomeration of Germanide. Therefore, the proposed Ni-Co alloy is promising for highly thermal immune Ni germanide for nano scale Ge-MOSFETs technology.

High-Efficiency Heterojunction with Intrinsic Thin-Layer Solar Cells: A Review

  • Dao, Vinh Ai;Kim, Sangho;Lee, Youngseok;Kim, Sunbo;Park, Jinjoo;Ahn, Shihyun;Yi, Junsin
    • Current Photovoltaic Research
    • /
    • v.1 no.2
    • /
    • pp.73-81
    • /
    • 2013
  • Heterojunction with Intrinsic Thin-layer (HIT) solar cells are currently an important subject in industrial trends for thinner solar cell wafers due to the low-temperature of production processes, which is around $200^{\circ}C$, and due to their high-efficiency of 24.7%, as reported by the Panasonic (Sanyo) group. The use of thinner wafers and the enhancement of cell performance with fabrication at low temperature have been special interests of the researchers. The fundamental understanding of the band bending structures, choice of materials, fabrication process, and nano-scale characterization methods to provide necessary understanding of the interface passivation mechanisms, emitter properties, and requirements for transparent oxide conductive layers is presented in this review. This information should be used for the performance characterization of the developing technologies for HIT solar cells.

Laser Micro-drilling of Sapphire/silicon Wafer using Nano-second Pulsed Laser (나노초 펄스 레이저 응용 사파이어/실리콘 웨이퍼 미세 드릴링)

  • Kim, Nam-Sung;Chung, Young-Dae;Seong, Chun-Yah
    • Journal of the Korean Society for Precision Engineering
    • /
    • v.27 no.2
    • /
    • pp.13-19
    • /
    • 2010
  • Due to the rapid spread of mobile handheld devices, industrial demands for micro-scale holes with a diameter of even smaller than $10{\mu}m$ in sapphire/silicon wafers have been increasing. Holes in sapphire wafers are for heat dissipation from LEDs; and those in silicon wafers for interlayer communication in three-dimensional integrated circuit (IC). We have developed a sapphire wafer driller equipped with a 532nm laser in which a cooling chuck is employed to minimize local heat accumulation in wafer. Through the optimization of process parameters (pulse energy, repetition rate, number of pulses), quality holes with a diameter of $30{\mu}m$ and a depth of $100{\mu}m$ can be drilled at a rate of 30holes/sec. We also have developed a silicon wafer driller equipped with a 355nm laser. It is able to drill quality through-holes of $15{\mu}m$ in diameter and $150{\mu}m$ in depth at a rate of 100holes/sec.