• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2018.05a
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• pp.155-155
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• 2018

In this study, we measured the communication performance of inductive coupler under high current condition. Ferrite and nanocrystalline cores were used to compare the available PLC communication range and bandwidth for current fluctuations.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.207-207
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• 2000

Multi- and single-wall carbon nanotubes are promising new carbon materials in nano-electronics, field-emitters, CRT-displays, hydrogen storage materials, biomedical tracers and so forth. The present talk will deal with a high-yield synthesis on quasi-aligned multi-wall carbon nanotubes via a chemical vapor deposition technique. I will also talk about a possible growth mechanism on single-wall carbon nanotubes based on newly obtained experimental results.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.122-123
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• 2007

Bias voltage를 달리하여 cathodic arc plasma 방법으로 Si 기판 위에 성장시킨 TiCrAlSiN 코팅막의 미세구조를 투과전자현미경으로 관찰하였다. -200 V에서 0 V로 bias voltage가 변화함에 따라 'nano-multilayered' 구조가 무너지면서 '주상형(columnar)'구조로 코팅막의 미세구조가 변함을 알 수 있었고, EDS line scan을 통해 multilayer의 화학적 조성 변화를 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.371-374
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• 2004

In this paper, Ni Germane-silicide formed on undoped $Si_{0.8}Ge_{0.2}$ as well as source/drain dopants doped $Si_{0.8}Ge_{0.2}$ was characterized by the four-point probe for sheet resistance. x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and field emission scanning electron microscope (FESEM). Low resistive NiSiGe is formed by one step RTP (Rapid thermal processing) with temperature range at $500{\~}700^{\circ}C$. To enhance the thermal stability of Ni Germane-silicide, Ni/Co/TiN structure with different Co concentration were studied in this work. Low sheet resistance was obtained by Ni/Co/TiN structure with high Co concentration using 2-step RTP and it almost keeps the same low sheet resistance even after furnace annealing at $650^{\circ}C$ for 30 min.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.9
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• pp.676-680
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• 2010

In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.2-291.2
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• 2016

3D semiconductor material of silicon that is used throughout the semiconductor industry currently faces a physical limitation of the development of semiconductor process technology. The research into the next generation of nano-semiconductor materials such as semiconductor properties superior to replace silicon in order to overcome the physical limitations, such as the 2-dimensional graphene material in 2D transition-metal dichalcogenide (TMD) has been researched. In particular, 2D TMD doping without severely damage of crystal structure is required different conventional methods such as ion implantation in 3D semiconductor device. Here, we study a p-type doping technique on tungsten diselenide (WSe2) for p-channel 2D transistors by adjusting the concentration of hydrochloric acid through Raman spectroscopy and electrical/optical measurements. Where the performance parameters of WSe2 - based electronic device can be properly designed or optimized. (on currents increasing and threshold voltage positive shift.) We expect that our p-doping method will make it possible to successfully integrate future layered semiconductor devices.

• ETRI Journal
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• v.37 no.1
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• pp.128-137
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• 2015

In this work, a fishbone-type transmission line employing a comb-type ground plane (FTLCGP) was fabricated on polyethersulfone (PES) substrate, and its RF characteristics were thoroughly investigated. According to the results, it was found that the FTLCGP on PES showed periodic capacitance values much higher than other types of transmission lines due to a coupling capacitance between the signal line and ground, which resulted in a reduction of wavelength and line width. Using the theoretical analysis, we also extracted the bandwidth characteristic of the FTLCGP on PES. According to the result, the FTLCGP structure showed a cut-off frequency of 280 GHz.