• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.147-155
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• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• 한국전산유체공학회:학술대회논문집
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• 2011.05a
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• pp.117-123
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• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.

• Journal of the Korea Society of Computer and Information
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• v.20 no.6
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• pp.1-11
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• 2015

Recently, NAND flash memories are used for storage devices because of fast access speed and low-power. However, applications of FTL on low power computing devices lead to heavy workloads which result in a memory requirement and an implementation overhead. Consequently, studies of B+-Tree on embedded devices without the FTL have been proposed. The studies of B+-Tree are optimized for performance of inserting and updating records, considering to disadvantages of the NAND flash memory that it can not support in-place update. However, if a general garbage collection method is applied to the previous studies of B+-Tree, a performance of the B+-Tree is reduced, because it generates a rearrangement of the B+-Tree by changing of page positions on the NAND flash memory. Therefor, we propose a novel garbage collection method which can apply to the B+-Tree based on the NAND flash memory without the FTL. The proposed garbage collection method does not generate a rearrangement of the B+-Tree by using a block information table and a proxy block. We implemented the B+-Tree and ${\mu}$-Tree with the proposed garbage collection on physical devices with the NAND flash memory. In experiment results, the proposed garbage collection scheme compared to greedy algorithm garbage collection scheme increased the number of inserted keys by up to about 73% on B+-Tree and decreased elapsed time of garbage collection by up to about 39% on ${\mu}$-Tree.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.171-178
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• 2015

Recently NAND flash memory has been found to be the primary cause of low performance in the smart device. NAND flash memory is different from each other the execution time of I/O operations that flash file system is required. Therefore, it is necessary to compare and analyze the flash file system I/O performance for the efficient I/O on smart device. In this paper, it was tested and analyzing the I/O performance of the YAFFS2, JFFS2, UBIFS. Experimental results most read I/O performance is good, but the writing I/O performance is not good. For UBIFS, showed a more good I/O performance compared to other flash file system.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.251-255
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• 2008

In most file systems, if a file is deleted, only the metadata of the file is deleted or modified and the file's data is still stored on the physical media. Some users require that deleted files no longer be accessible. This requirement is more important in embedded systems that employ flash memory as a storage medium. In this paper, we propose a secure deletion method for NAND flash file system and apply the method to YAFFS. Our method uses encryption to delete files and forces all keys of a specific file to be stored in the same block. Therefore, only one erase operation is required to securely delete a file. Our simulation results show that the amortized number of block erases is smaller than the simple encryption method. Even though we apply our method only to the YAFFS, our method can be easily applied to other NAND flash file systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.246-254
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• 2022

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.47-57
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• 2008

Recently, energy-efficient NAND Flash memory of large volume is favored as next-generation storage for sensor nodes. So far, most sensor node file systems are based on NOR flash and few file systems are applicable to large NAND flash memory. Although it is required to develop new file systems taking account of the features of NAND flash memory, it is difficult to develop them mainly due to the limit of SRAM memory on sensor nodes. Sensor nodes support SRAM of $4{\sim}10$ KBytes only. In this paper, we designed and implemented a novel file system to support data-centric applications. To do this, we added EEPROM of 1 KBytes to store persistent file description data efficiently and devised a simple wear-leveling method. This reduces the number of page updates, resulting in reduction in energy use and increase in lifetime of sensor nodes.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.184-193
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• 2007

Flash memory adoption in the mobile devices is increasing or vanous multimedia services such as audio, videos, and games. Although the traditional research issues such as out-place update, garbage collection, and wear-leveling are important, the performance, memory usage, and fast mount issues of flash memory file system are becoming much more important than ever because flash memory capacity is rapidly increasing. In this paper, we address the problems of the existing log-based flash memory file systems analytically and propose an efficient log-based file system, which produces higher performance, less memory usage and mount time than the existing log-based file systems. Our ideas are applied to a well-known log-based flash memory file system (YAFFS2) and the performance tests are conducted by comparing our prototype with YAFFS2. The experimental results show that our prototype achieves higher performance, less system memory usage, and faster mounting than YAFFS2, which is better than JFFS2.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.7
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• pp.515-519
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• 2009

As the application fields of sensor nodes are getting diverse these days, it is required to have a way of collecting various data that is suitable for these application fields. In the case that the real-time surveillance over the data is unnecessary, present data collecting methods, which collect and transfer the data directly, can cause a waste of energy and data loss, A new method that store the collected data in a local storage and acquire them by query later on is required for nonreal-time applications. NAND flash has energy efficiency and large capacity so it is suitable for sensor nodes, Sensor nodes support 4-10 KBytes small sized memory and it is hard to build an effective file system since NAND Flash doesn't support overwriting NAND flash. This paper discusses an implementation of NAND Flash file system in sensor node environments. The file system makes long-term data collecting possible by reducing transmission cost. It is expected that this file system will play a central role in sensor network environments as it can be applied to various fields which call for long term data collecting.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.333-337
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• 2007

Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.