• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.105-106
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• 2017

본 논문은 10kW급 태양광 3 레벨 NPC 인버터 설계에 대해 서술하였다. 3 레벨 인버터는 2 레벨 인버터보다 정격 전압과 출력전류의 고조파 감소가 가능하기 때문에 효율이 높다는 장점이 있다. 설계된 태양광 3 레벨 인버터는 제어보드, 게이트보드, 3 레벨 IGBT 등으로 구성된다. 게이트 드라이버 보드는 소자들의 최소 절연거리와 신호전달의 용이성을 고려하여 설계되었다. 3 레벨 NPC 인버터의 동작을 PSIM을 통해 시뮬레이션 하였으며, 실험을 통하여 제작된 태양광 3 레벨 인버터가 실제 조건에서도 정상적으로 동작함을 검증하였다.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.356-357
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• 2011

3-레벨 중성점 다이오드 클램프 (NPC) 인버터는 우수한 토폴로지로 알려져 있지만 구조적으로 중성점 전위가 변동하는 문제가 내제하고 있다. 본 논문에서는 3-레벨 NPC 인버터 중 성점 전압의 변동을 제어하기 위해 중성점 전류의 예측을 활용한 간단한 제어 기술이 제안되었다. 제안된 방법은 한 샘플링 앞선 시점의 중성점 전류를 예측하고 중성점 평형 요소를 포함하는 오프셋 전압(Voffset)을 이용하여 중성점 전압을 제어 한다. 중성점 전위 변동은 간단히 제어할 수 있고 제안된 중성점 전압 제어의 유효함은 시뮬레이션 결과를 통해 입증하였다.

• Journal of Power Electronics
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• v.5 no.3
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• pp.224-232
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• 2005

A new three phase three-level Pulse Width Modulation (PWM) Switched Voltage Source (SVS) inverter with zero neutral point potential is proposed. It consists of three single-phase inverter modules. Each module is composed of a switched voltage source and inverter switches. The major advantage is that the peak value of the phase output voltage is twice as high as that of a conventional neutral-point-clamped (NPC) PWM inverter. Thus, the proposed inverter is suitable for applications with low voltage sources such as batteries, fuel cells, or solar cells. Furthermore, three-level waveforms of the proposed inverter can be achieved without the switch voltage imbalance problem. Since the average neutral point potential of the proposed inverter is zero, a common ground between the input stage and the output stage is possible. Therefore, it can be applied to a transformer-less Power Conditioning System (PCS). The proposed inverter is verified by a PSpice simulation and experimental results based on a laboratory prototype.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Journal of Power Electronics
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• v.19 no.1
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• pp.146-157
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• 2019

The inverter is an essential part of permanent magnet synchronous motor (PMSM) drive systems. The performance of an inverter is greatly influenced by its modulation strategy. Using a proper management of modulation strategies can guarantee high performance from a PMSM under various speed conditions. Switching between modulations is a pivotal technique that determines the performance of a PMSM. Most works on hybrid methods focus on two-level induction motors drive systems. In this paper, in order to improve the performance of PMSMs under various speed conditions, a hybrid method of a pulse width modulation (PWM) control scheme based on a neutral-point-clamped (NPC) three level topology was proposed. This hybrid PWM modulation comprised space vector PWM (SVPWM) and selective harmonic elimination PWM (SHEPWM). Under low speed conditions, the SVPWM is employed to cause the PMSM to start smoothly, and to obtain a rapid response from the control system. Under high speed conditions, the SHEPWM is employed to reduce the switching frequency and to eliminate particular current harmonics. Moreover, the harmonic characteristics of different modulations are analyzed to obtain a smooth transition between the SHEPWM and the SVPWM. Experimental and simulation results indicated the effectiveness of the proposed control method.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.459-462
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• 2019

This work presents methods for reducing overshoot voltages across the drain-source of silicon carbide (SiC) MOSFETs in grid-connected hybrid active neutral-point-clamped (ANPC) inverters. Compared with 3-level NPC-type inverter, the hybrid ANPC inverter can realize the high efficiency. However, SiC MOSFETs conduct its switching operation at high frequencies, which cause high overshoot voltages in such devices. These overshoot voltages should be reduced because they may damage switching devices and result in electromagnetic interference (EMI). Two major strategies are used to reduce the overshoot voltages, namely, adjusting the gate resistor and using a snubber capacitor. In this paper, advantages and disadvantages of these methods will be discussed. The effectiveness of these strategies is verified by experimental results.

• Journal of Power Electronics
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• v.12 no.2
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• Journal of Power Electronics
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• v.11 no.4
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• pp.583-590
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• 2011

Three-level NPC inverters have been put into practical use for years especially in high voltage high power grids. This paper researches three-level active power filters (APFs). In this paper a mathematical model in the d-q coordinates is presented for 3-phase 3-wire NPC APFs. The deadbeat control scheme is obtained by using state equations. Canceling the delay of one sampling period and providing the predictive value of the harmonic current is a key problem of the deadbeat control. Based on this deadbeat control, the predictive output current value is obtained by the state observer. The delay of one sampling period is remedied in this digital control system by the state observer. The predictive harmonic command current value is obtained by the repetitive predictor synchronously. The repetitive predictor can achieve a better prediction of the harmonic current with the same sampling frequency, thus improving the overall performance of the system. The experiment results indicate that the steady-state accuracy and the dynamic response are both satisfying when the proposed control scheme is implemented.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.11-16
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• 2003

The 3-level converter/inverter system is very efficient in the ac motor drives of high voltage and high power application. This paper proposed a simple method to diagnose faults using change of current vector pattern in space vector diagram when the faults occurrence in the 3-level inverter and a control method that can protect system from unbalance of the neutral point voltage according to faults. The validity of the proposed method is demonstrated by the simulation results.

• Journal of Power Electronics
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• v.18 no.1
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• pp.70-80
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• 2018

A novel strategy based on a zero common mode voltage pulse-width modulation (ZCMV-PWM) technique and zero-sequence circulating current (ZSCC) feedback control is proposed in this study to eliminate ZSCCs between three-level neutral point clamped (NPC) voltage source inverters, with common AC and DC buses, that are operating in parallel. First, an equivalent model of ZSCC in a three-phase three-level NPC inverter paralleled system is developed. Second, on the basis of the analysis of the excitation source of ZSCCs, i.e., the difference in common mode voltages (CMVs) between paralleled inverters, the ZCMV-PWM method is presented to reduce CMVs, and a simple electric circuit is adopted to control ZSCCs and neutral point potential. Finally, simulation and experiment are conducted to illustrate effectiveness of the proposed strategy. Results show that ZSCCs between paralleled inverters can be eliminated effectively under steady and dynamic states. Moreover, the proposed strategy exhibits the advantage of not requiring carrier synchronization. It can be utilized in inverters with different types of filter.