• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• 전기학회논문지
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• 제64권2호
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• pp.268-275
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• 2015

This paper proposes a method of switching to improve power loss for the single-phase three-level NPC inverter. The conventional switching methods, which are called as the bipolar and unipolar switching methods, are used for single phase inverters using three-level topology. However, these switching method have disadvantage in the power loss. Because all of the switch are operated. To reduce the power loss of the three-level NPC inverter, clamp switching method is introduced in this paper. This way, one of the lag is fixed that switching loss is reduced. This paper analyzes and compares power losses of unipolar method and clamp method. The validity of the power loss analysis is verified through the simulation and experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.487-488
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• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• 전력전자학회논문지
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• 제19권3호
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• pp.257-265
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• 2014

This paper proposes a simple compensation method for switches of the unclamped voltage in the three-level NPC inverter. Voltages of inner-switches can be unclamped in the three-level NPC (neutral point clamped) inverter. It can cause the problem of the switch fault accident. By adding a capacitor, switches of the unclamped voltage can be clamped. Through the analysis of the circuit, the reason behind switches being unclamped was verified which leads to the solution method that designs a compensation capacitor. The proposed method was validated through the simulation and experimental results.

• Journal of Power Electronics
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• 제15권1호
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• pp.106-115
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• 2015

This paper proposes a novel direct power control (DPC) strategy for neutral-point-clamped (NPC) three-level rectifiers, to directly control the active power, the reactive power and the neutral point potential of the rectifiers by referring to three pre-calculated vector influence tables and minimizing an objective function. In the three vector influence tables, the influences of different voltage vectors on the active power, the reactive power and the neutral-point potential are shown explicitly. A conceptual description and control algorithm of the proposed controller are presented in this paper. Then, numerical simulations and experiments are carried out to validate the proposed method. Both the simulation and experimental results show that good performances during both the steady-state and transient operating conditions are achieved. As a result, the proposed strategy has been proven to be effective for NPC three-level rectifiers.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• 전력전자학회논문지
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• 제19권4호
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• 전기학회논문지
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• 제66권5호
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• pp.778-785
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• 2017

This paper presents a control method for reducing the distortion of the grid current at a grid-connected three-level neutral point clamped (NPC) inverter. The grid current is distorted from the 5th and 7th harmonic components in the stationary frame current also the 6th harmonic component in the synchronous frame current. In this paper, the 6th harmonic component on synchronous frame is controlled by using all-pass filters (APFs) and proportional integral (PI) controllers for distortion of the grid side. When transformed the 6th harmonic component is controlled, the 5th and 7th harmonic components are reduced. The validity of the proposed control method is verified by simulation and experiment results using a 25kW three-level NPC inverter.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.489-500
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• 2014

This paper presents a simple modified unipolar carrier-based pulsewidth modulation (CB-PWM) strategy for the three-level neutral-point-clamped (NPC) voltage source inverter (VSI). Analytical expressions for the relationship between modulation reference signals and output voltages are derived. The proposed modulation technique for the three-level NPC VSI includes the maximum and minimum of the three-phase sinusoidal reference voltages with zero-sequence voltage injection concept. The proposed modified CB-PWM strategy incorporates a novel method that requires only of one triangular carrier wave for generate the gating pulses in three-level NPC VSI. It has the advantages of being simplifying the algorithm with no need of complex two/multi-carrier pulsewidth modulation or space vector modulation (SVM) and it's also simple to implement. The possibility of the proposed CB-PWM technique has been verified though computer simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제8권3호
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• pp.544-558
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• 2013

This paper proposes a simplified and efficient control scheme for Unified Power Quality Conditioner (UPQC) based on three-level (NPC) inverter capable to mitigate source current harmonics and compensate all voltage disturbances perturbations such us, voltage sags, swells, unbalances and harmonics. The UPQC is designed by the integration of series and shunt active filters (AFs) sharing a common dc bus capacitor. The dc voltage is maintained constant using proportional integral voltage controller. The shunt and series AF are designed using a three-phase three-level (NPC) inverter. The synchronous reference frame (SRF) theory is used to get the reference signals for shunt and the power reactive theory (PQ) for a series APFs. The reference signals for the shunt and series APF are derived from the control algorithm and sensed signals are injected in tow controllers to generate switching signals for series and shunt APFs. The performance of proposed UPQC system is evaluated in terms of power factor correction and mitigation of voltage, current harmonics and all voltage disturbances compensation in three-phase, three-wire power system using MATLAB-Simulink software and SimPowerSystem Toolbox. The simulation results demonstrate that the proposed UPQC system can improve the power quality at the common connection point of the non-linear load.