• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.209-210
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• 2011

본 논문은 3레벨 NPC 인버터의 중성점 전위 변동 시 퍼지제어기를 이용한 중성점 전위 제어 방법을 제안한다. 오프셋 전압을 퍼지제어기의 입력으로 하여 공간벡터의 스위칭 타이밍의 조절변수를 출력함으로써 기존의 오프셋 전압의 복잡한 수학적 모델링 없이 쉽고 간단하게 중성점 전압을 제어한다. 제안하는 제어기법의 우수성을 보이기 위하여 10kW급 계통연계 3-레벨 NPC인버터 모델을 기반으로 시뮬레이션을 수행하였다.

• 전력전자학회논문지
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• 제22권2호
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• pp.118-125
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• 2017

In this paper, we propose a smart transformer for a smart transformer miniature model, which can replace a 60 [Hz] single-phase transformer installed in an electric vehicle. The proposed smart transformer is lighter than a conventional transformer, can control instantaneous voltage, and can be expected to improve power quality through harmonic compensation. The proposed intelligent transformer consists of an incoming part, an AC/DC converter, and a dual active bridge. Only the incoming part and the AC/DC converter are described in this paper. The proposed intelligent transformer has 75 kVA 3.3 kV input and 750 V DC output, which are verified by simulation and experiment.

• Journal of Power Electronics
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• 제19권1호
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• pp.108-118
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• 2019

This paper proposes a DC-link voltage balance controller using the fourth-phase of a three-level neutral-point clamped (NPC) PWM converter with medium vector selection (MVS) PWM for common-mode voltage reduction. MVS PWM makes the voltage reference by synthesizing the voltage vectors that cannot generate common-mode voltage. This PWM method is effective for reducing the EMI noise emitted from converter systems. However, the DC-link voltage imbalance problem is caused by the use of limited voltage vectors. Therefore, in this paper, the effect of MVS PWM on the DC-link voltage of a three-level NPC converter is analyzed. Then a proportional-derivative (PD) controller for the DC-link voltage balance is designed from the DC-link modeling. In addition, feedforward compensation of the neutral point current is included in the proposed PD controller. The effectiveness of the proposed controller is verified by experimental results.

• Journal of Power Electronics
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• 제15권5호
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Journal of Power Electronics
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• 제12권2호
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• pp.344-356
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• 2012

In recent years, multilevel technology has become an effective and practical solution in the field of moderate and high voltage applications. This paper discusses an APF with a three-level NPC inverter. Obviously, the application of such converter to APFs is hindered by the problem of the voltage unbalance of DC capacitors, which leads to system instability. This paper comprehensively analyzes the theoretical limitations of the neutral-point voltage balancing problem for tracking different harmonic currents utilizing current switching functions from the space vector PWM (SVPWM) point of view. The fluctuation of the neutral point caused by the load currents of certain order harmonic frequency is reported and quantified. Furthermore, this paper presents a close-loop digital control algorithm of the DC voltage for this APF. A PI controller regulates the DC voltage in the outer-loop controller. In the current-loop controller, this paper proposes a simple neutral-point voltage control method. The neutral-point voltage imbalance is restrained by selecting small vectors that will move the neutral-point voltage in the direction opposite the direction of the unbalance. The experiment results illustrate that the performance of the proposed approach is satisfactory.

• Journal of Power Electronics
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• 제14권3호
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• pp.519-530
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• 2014

A novel simplified pulse width modulation(PWM) strategy for neutral point clamped (NPC) three-level converter is proposed in this paper.The direct output voltage modulation is applied to reduce the calculation time. Based on this strategy, several optimized control methods are proposed. The neutral point potential balancing algorithm is discussed and a fine neutral point potential balancing scheme is introduced. Moreover, the minimum pulse width compensation and switching losses reduction can be easily achieved using this modulation strategy. This strategy also gains good results even with the unequal DC link capacitor. The modulation principle is studied in detail and the validity of this simplified PWM strategy is experimentally verified in this paper. The experiment results indicated that the proposed PWM strategy has excellent performance, and the neutral point potential can be balanced well with unequal DC link captaincies.

• Journal of Power Electronics
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• 제17권6호
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• pp.1500-1511
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• 2017

The purpose of this paper is to study a high-performance control scheme for neutral-point-clamping three-level (NPC-3L) inverter fed dual three-phase permanent magnet synchronous motor (PMSM) drives by considering some asymmetric factors such as the non-identical parameters in phase windings. To implement this, the system model is analyzed for dual three-phase PMSM drives with asymmetric factors based on the vector space decomposition (VSD) principle. Based on the equivalent circuits, PI controllers with feedforward compensation are used in the d-q subspace for regulating torque, where the cut-off frequency of the PI controllers are set at the twice the fundamental frequency for compensating both the additional DC component and the second order component caused by asymmetry. Meanwhile, proportional resonant (PR) controllers are proposed in the x-y subspace for suppressing the possible unbalanced currents in the phase windings. A dual three-phase space vector modulation (DT-SVM) is designed for the drive, and the balancing factor is designed based on the numerical fitting surface for balancing the DC link capacitor voltages. Experimental results are given to demonstrate the validity of the theoretical analysis and the proposed control scheme.

• BMB Reports
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• 제48권9호
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• pp.513-518
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• 2015

Factors that modulate cholesterol levels have major impacts on cardiovascular disease. Niemann-Pick C1-like 1 (NPC1L1) functions as a sterol transporter mediating intestinal cholesterol absorption and counter-balancing hepatobiliary cholesterol excretion. The liver receptor homolog 1 (LRH-1) had been shown to regulate genes involved in hepatic lipid metabolism and reverse cholesterol transport. To study whether human NPC1L1 gene is regulated transcriptionally by LRH-1, we have analyzed evolutionary conserved regions (ECRs) in HepG2 cells. One ECR was found to be responsive to the LRH-1. Through deletion studies, LRH-1 response element was identified and the binding of LRH-1 was demonstrated by EMSA and ChIP assays. When SREBP2, one of several transcription factors which had been shown to regulate NPC1L1 gene, was co-expressed with LRH-1, synergistic transcriptional activation resulted. In conclusion, we have identified LRH-1 response elements in NPC1L1 gene and propose that LRH-1 and SREBP may play important roles in regulating NPC1L1 gene. [BMB Reports 2015; 48(9): 513-518]

• Journal of Power Electronics
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• 제13권2호
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• pp.243-249
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• 2013

This paper presents a neutral-point voltage balancing method for three-level inverter systems using a time-offset estimation scheme. The neutral-point voltage is balanced by adding a time-offset to the turn-on time of the switches. If an inaccurate time-offset is added, the neutral-point deviation still remains. An accurate time-offset is obtained through the proposed time-offset estimation scheme. This method is implemented without additional hardware, complex calculations, or analysis. The effectiveness of the proposed method is verified by experiments.

• Journal of Power Electronics
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• 제14권2호
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• pp.315-323
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• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.