• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.35-39
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• 2019

The shielding effectiveness (SE) of the EMI spray coating film was measured in a three-dimensional structure. The shielding effectiveness was measured by AST D4935 using coaxial type TEM cell. A standard sample of the cylindrical slab is fabricated to measure the shielding effectiveness using the ASTM D4935. At this time, spray coating was performed by bonding a three-dimensional structure with NAND flash memory to a standard sample. In the case of spray coating, it was uniformly coated not only on the horizontal plane but also on the vertical plane of the three-dimensional structure. As a result of measurement, shielding effectiveness of maximum 59 dB was measured in a three-dimensional structure similar to the case without three-dimensional structure. As a result, it was confirmed that the spray coating can be uniformed even in the three-dimensional structure.

• Journal of Digital Convergence
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• v.20 no.5
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• pp.593-598
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• 2022

Recently, data production has seen explosive growth, and the storage systems to store these big data safely and quickly is evolving in various ways. A typical configuration of storage systems is the use of SSDs with fast data processing speed as a RAID group that can maintain reliable data. However, since NAND flash memory, which composes SSD, has the feature that deterioration if writes more than a certain number of times are repeated, can increase the likelihood of simultaneous failure on multiple SSDs in a RAID group. And this can result in serious reliability problems that data cannot be recovered. Thus, in order to solve this problem, we propose a method of throttling IOs so that each SSD within a RAID group leads to a different life-end. The technique proposed in this paper utilizes SMART to control the state of each SSD and the number of IOs allocated according to the data pattern used step by step. In addition, this method has the advantage of preventing large amounts of concurrency defects in RAID because it induces differential lifetime finishes of SSDs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.7
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• pp.425-432
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• 2014

This paper proposes a wear-leveling algorithm that exploits the properties of SSD memories with multi-channel and multi-way architecture. When a write request arrives, the proposed algorithm classifies the stored data in DRAM buffer into hot or cold according to logical address access frequency, and performs data allocation to reduce deviation of block erase counts. It lowers the chance of increasing erase count by allocating cold data to blocks which have high erase count. Effectiveness of the proposed algorithm is verified by executing various applications on a multi-channel, multi-way SSD simulator. Experimental results show that differences in erase count among blocks is reduced by an average of 9.3%, and total erase count decreases by 4.6%, when compared to previous wear-leveling algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.36-42
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• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06c
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• pp.69-74
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• 2007

플래시 메모리는 하드디스크와 다른 물리적 특성을 가지고 있다. 대표적으로 덮어쓰기가 되지 않고 데이터를 읽고 쓰는 단위와 지우는 단위가 서로 다르다. 이러한 물리적 제약을 소프트웨어적으로 보완해주기 위해서 플래시 메모리를 사용하는 시스템에서는 대부분 Flash Translation Layer (FTL)을 사용한다. 지금까지 FTL 알고리즘의 대부분이 임의 쓰기 패턴보다 순차 쓰기 패턴에 훨씬 더 효율적으로 작용한다. 그러나 B-트리와 같은 자료구조에서는 일반적으로 순차 쓰기 패턴 보다는 임의 쓰기 패턴이 발생된다. 따라서 플래시 메모리상에서 B-트리를 관리할 경우 FTL에 비효율적인 쓰기 패턴을 생성하게 된다. 본 논문에서는 플래시 메모리상에서 B-트리와 같은 자료구조를 효율적으로 저장 관리하기 위한 새로운 방식을 제안한다. 새로운 방식은 B-트리에서 발생되는 임의 쓰기를 플래시 메모리상의 버퍼를 이용하여 FTL에 효율적인 순차 쓰기를 발생시킨다. 실험 결과, 본 논문에서 제안하는 방식은 기존의 방식보다 플래시 메모리에서 발생되는 쓰기 및 블록소거 연산 횟수를 60%이상 감소시킨다.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.329-330
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• 2008

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.647-650
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• 2009

IPTV(Internet Protocol Television)는 차별화된 초고속 광대역 네트워크를 기반으로 기존 TV의 단점을 보완하여 차세대 DTV 시장을 주도할 것으로 예상된다. IPTV의 저장용량이 증가하는 추세에 따라 SSD(Solid State Disk)가 NAND 플래시 메모리를 대체 할 것으로 예상된다. 본 논문에서는 IPTV의 저장장치인 SSD의 수명을 증가시키고 플래시메모리의 특성인 마모도 제한을 고려하지 않은 지움 정책(Garbage-Collection)을 사용하는 YAFFS(Yet Another Flash FileSystem)의 문제점을 해결하기 위해 블록을 내용기반 리스트로 관리하고 블록스왑을 사용하는 내용기반 지움 정책을 제안한다. 기존 파일시스템 보다 수명을 향상 시키는 내용기반 파일시스템을 설계 및 구현하여 성능을 분석하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.914-916
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• 2011

최근 낸드 플래시 메모리 기술의 발전으로 플래시 메모리의 용량이 증가함에 따라 다양한 장치에서 데이터 저장소로 사용되고 있으며, 하드디스크를 대체할 저장 매체로서 주목을 받고 있다. 하지만 낸드 플래시 메모리의 특성으로 인해 데이터를 삭제하더라도 일정 기간 삭제된 데이터가 메모리에 남아있게 되며, 이러한 특성으로 사용자의 중요 데이터가 보호되지 않은 상태로 저장되어 외부에 노출될 수 있다. 따라서 이런 특성을 보완하는 방법이 필요하며 본 논문에서는 낸드 플래시 메모리의 단점을 해결하기 위하여 낸드 플래시 메모리를 위한 시스템 소프트웨어인 FTL(Flash Translation Layer) 계층에서 암호화 알고리즘을 사용하여 데이터를 노출하지 않게 하는 방법을 제안한다.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.